SAA7390 Datasheet, PDF (45/76 Pages) NXP Semiconductors – High performance Compact Disc-Recordable CD-R controller

Philips Semiconductors
High performance Compact
Disc-Recordable (CD-R) controller
Preliminary specification
SAA7390
Table 66 CSTS field descriptions
FIELD
SAR
NRQ⁽¹⁾
RDY⁽²⁾
ACA
LBT
HEF
ATT⁽⁴⁾
LOGIC
DESCRIPTION
0 status not ready yet during this block; SAR cleared on each new block
1 status already read
0 no request to host will be issued
1 requests to host will be issued
0 data block transmission is in progress
1 data transmission is ceased
0 access to CDB2 is denied
1 access to CDB2 is allowed
0 state of block counter has reached zero
1 block counter is non zero
0 no error has occurred during communication with the host
1 an error has occurred in the host communication process; note 3
0 interrupt to microcontroller is asserted
1 no pending interrupts
Notes
1. Normally NRQ is LOW during synchronization, header and EDC/ECC transmission.
2. RDY is set after command bit ACT is pulled LOW.
3. This is a fatal error which can be rectified only by restarting CDB2.
4. Interrupt sources are ACA = logic 1, LBT = logic 0 and HEF = logic 1.
Table 67 Block count registers: 0xF0D3 and 0xF0D4; note 1
DATA BYTE
MNEMONIC R/W
7
6
5
4
3
2
1
0
CBCL
R/W
BLOCKCOUNT7 to BLOCKCOUNT0
CBCH
R/W
BLOCKCOUNT15 to BLOCKCOUNT8
Note
1. This is a 16-bit down counter which should be programmed with the; number of blocks - 1. As soon as the count value
reaches zero, LBT is cleared and ATT is pulled LOW. LBT remains active for 13.3 ms at single speed record. Note
that the counter continue to decrement. New programmed information is used at the start of the next block.
Table 68 Header containing MSF address and mode: 0xF0D5, F0D6, F0D7 and F0DB
DATA BYTE
MNEMONIC R/W
7
6
5
4
3
2
CMDE
R/W
−
−
−
−
−
−
CMIN
R/W
MINUTES7 to MINUTES0
CSEC
R/W
SECONDS7 to SECONDS0
CFRM
R/W
FRAME7 to FRAME0
1
0
MODE1 MODE0
1996 Jul 02
45