SAA7390 Datasheet, PDF (18/76 Pages) NXP Semiconductors – High performance Compact Disc-Recordable CD-R controller

Philips Semiconductors
High performance Compact
Disc-Recordable (CD-R) controller
Preliminary specification
SAA7390
Table 3 ECCSTAT definitions
MNEMONIC
DESCRIPTION
ECC_ACT asserted while a command other than ASSERT_ABORT or RELEASE_ABORT remains active
QS_EQ0 asserted when all Q syndromes are zero
PS_EQ0
asserted when all P syndromes are zero
CRC_EQ0 asserted when the CRC remainder calculated by the CRC_CALCULATE command is all zeros
FLG_EQ0 asserted when all flag bytes in ECC RAM are zero
8.2 Microcontroller interface command register
Table 4 ECCCTL register: 0xF085; note 1
MNEMONIC
R/W
7
6
5
ECCCTL
R/W
−
−
−
Note
1. The ECC_COMMAND definitions are explained in Table 5.
DATA BYTE
4
3
2
1
0
−
ECC_COMMAND3 to ECC_COMMAND0
Table 5 Definitions of ECC_COMMAND3 to ECC_COMMAND0
EEC_COMMAND
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1100
1101
1110
DESCRIPTION
ASSERT_ABORT
RELEASE_ABORT
CALCULATE_SYNDROMES (not Mode 2, Form 1)
CALCULATE_SYNDROMES (Mode 2, Form 1)
CRC_RECALCULATE (not Mode 2, Form 1)
CRC_RECALCULATE (Mode 2, Form 1)
COPY_RESULTS (not Mode 2, Form 1)
COPY_RESULTS (Mode 2, Form 1)
CORRECT_P_SYNDROMES
CORRECT_Q_SYNDROMES
TEST_ECC_ROM
TEST_ECC_RAM_READ
TEST_ECC_RAM_WRITE
Table 6 Command descriptions
COMMAND
ASSERT_ABORT
RELEASE_ABORT
DESCRIPTION
Terminates any currently active operation and re-initializes the ECC logic. Remains in
reset state until occurrence of the RELEASE_ABORT command. At power-on reset,
the ECC is in the ASSERT_ABORT state. All microprocessor status bits are reset
when the ECC is in the ASSERT_ABORT state.
Terminates the ASSERT_ABORT command and enables activation of other
commands.
1996 Jul 02
18