SAA7381 Datasheet, PDF (41/108 Pages) NXP Semiconductors – ATAPI CD-R block decoder

Philips Semiconductors
ATAPI CD-R block decoder
Objective specification
SAA7381
Table 64 Description of the ‘trant’ bits
trant
(bits 2 to 0)
000
001
010
011
100
101
11X
FROM
−
host
microcontroller
memory
host
microcontroller
reserved
TO
host
memory
memory
microcontroller
microcontroller
host
reserved
MAXIMUM
BYTES
NOTES
65535 maximum bytes for auto sequence DMA is
(ATAPI, PIO) 4.3 Gbytes
65535 maximum bytes for auto sequence DMA is
(ATAPI, PIO) 4.3 Gbytes
−
redundant
−
redundant
12
PIO; DBC not used, always 12 bytes
12
DMA and PIO
reserved −
7.5.3.12 ADRSEL
This is the ATAPI drive select register.
Table 65 ADRSEL: address FF8CH
ACCESS
RW
BIT 7
1
BIT 6
1
BIT 5
1
BIT 4
drv⁽¹⁾
BIT 3
−
BIT 2
−
BIT 1
−
BIT 0
−
Note
1. Bit 4 of this register is the ‘drv’ bit. When this bit is the same as the ‘rdrv’ bit in the DTCTR register then the SAA7381
will be the selected ATAPI drive and will respond to commands and produce interrupts. The host interrupt pin will
also be enabled when the SAA7381 is the selected drive.
7.5.3.13 AINTR
This is the ATAPI interrupt reason register. See the ATAPI specification for a detailed description of these register bits.
Table 66 AINTR: address FF8DH
ACCESS
RW
BIT 7
−
BIT 6
−
BIT 5
−
BIT 4
−
BIT 3
−
BIT 2
release
BIT 1
io
BIT 0
cod
7.5.3.14 AERR
This is the ATAPI error register. See the ATAPI specification for a detailed description of these register bits.
Table 67 AERR: address FF8EH
ACCESS
RW
BIT 7
BIT 6
BIT 5
sense key
BIT 4
BIT 3
mcr
BIT 2
abrt
BIT 1
eom
BIT 0
−
1997 Aug 12
41