SAA7381 Datasheet, PDF (29/108 Pages) NXP Semiconductors – ATAPI CD-R block decoder

Philips Semiconductors
ATAPI CD-R block decoder
Objective specification
SAA7381
7.3.4 IEC 958/EBU OUTPUT
Table 39 Description of the IECCTRL register control bits (notes 1 and 2)
BIT
7
6
5
4
3
2
1 to 0
NAME
iecen
data
copyright
preem
vbit
−
accu
VALUE
0
1
0
1
0
1
0
1
0
1
−
−
00
01
10
11
DESCRIPTION
IEC 958 interface is off
IEC 958 Interface is on
IEC 958 contains audio information
IEC 958 contains data
IEC 958 C bit in system channel is logic 0
IEC 958 C bit in system channel is logic 1
audio pre-emphasis off/IEC 958 contains data
audio pre-emphasis on (only appears in IEC 958 C channel;
de-emphasis bit is not implemented in the SAA7381)
audio samples suitable for conversion
mute audio, or signal is data and should not be digital-to-analog
converted at any time
reserved
reserved
level II clock accuracy
level III clock accuracy (depends on mck/system clock)
reserved
reserved
Notes
1. In order for the IEC interface to operate correctly, it will require a clock at 128f_s to be present.
2. The ‘vbit’ is copied into the V bit of the IEC 958 frame.
Table 40 IEC 958 system channel bit mapping (note 1)
BIT NUMBER
0
8
16
24
BIT OFFSET
+0
+1
+2
+3
+4
+5
+6
+7
0
data copyright preem
−
0
0
0
cat0
cat1
cat2
cat3
cat4
cat5
cat6
cat7
0
0
0
0
0
0
0
0
0
0
0
0
accu0 accu1
0
0
Note
1. The C bit is updated on an IEC frame-by-frame basis, the bit offset corresponds to the IEC frame offset. They are
repeated for both left and right channels. Bit 0 is present in the C bit of the first sample pair of the IEC superframe of
192 sample pairs.
1997 Aug 12
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