SAA7381 Datasheet, PDF (38/108 Pages) NXP Semiconductors – ATAPI CD-R block decoder

Philips Semiconductors
ATAPI CD-R block decoder
Objective specification
SAA7381
7.5.3 DESCRIPTION OF THE HOST INTERFACE REGISTERS
This section describes the operation of the register bits in the SAA7381 host interface block.
7.5.3.1 ADATA
This is a 12-byte FIFO used to transfer data from the microcontroller to the host. To transfer data the ‘trant’ bits (0 to 2)
of the DTCTR register must be set to 101.
7.5.3.2 IFCTRL
Table 57 IFCTRL: address FF81H (note 1)
ACCESS
RW
BIT 7
cmdien
BIT 6
dteien
BIT 5
drqien
BIT 4
ultra_stopien
BIT 3
−
BIT 2
srstien
BIT 1
−
BIT 0
−
Note
1. Bits ‘cmdien’, ‘dteien’, ‘drqien’ and ‘ultra_stopien’, are the enable bits for interrupt bits ‘cmdi’, ‘dtei’, ‘drqi’ and
‘ultra_stop’ in the IFSTAT register. These are interrupt masks, enabling/disabling the microcontroller interrupt pin.
They do not affect the bits in the IFSTAT register. If set to logic 1, the corresponding interrupt is enabled. It should
be noted that these masks do not clear the interrupts. Bit 2 (srstien) is asserted at power-on reset, enabling the ‘srsti’
interrupt. If set to logic 1 the ‘srsti’ interrupt is disabled.
7.5.3.3 DBCL and DBCH
These are the ATAPI byte count registers. DBCL is the lower byte (bits 7 to 0) register and DBCH is the higher byte
(bits 15 to 8) register. These registers are read/writable for both the PC host and microcontroller.
Table 58 ATAPI byte count registers; addresses FF82H (DBCL) and FF83H DBCH)
ACCESS
RW
RW
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Data Byte Count register bits (bits 7 to 0)
Data Byte Count register bits (bits 15 to 8)
BIT 1
BIT 0
The data byte counter is used by the microcontroller to control the number of bytes that are transferred during a data
transfer. During memory-to-host data transfers the data byte counter is decremented after every host read. During
host-to-memory data transfers the data byte counter is decremented as data is written into the external buffer memory.
The host may write to DBCL/DBCH to indicate to the microcontroller the maximum transfer/reception length, which may
be updated by the auto sequencer PACKETSIZE STORE registers or from the TRANSFER COUNTER (for the
remainder packet size) or directly by the microcontroller. The host can then read back the updated byte count to be
transferred.
7.5.3.4 DTRG
Writing to this register starts a data transfer. The data written is discarded.
7.5.3.5 DTACK
Writing to this register clears the DTEI interrupt and the ‘A0comp/crc_error’ flag. The data written is discarded.
1997 Aug 12
38