UMA1020M Datasheet, PDF (4/20 Pages) NXP Semiconductors – Low-voltage dual frequency synthesizer for radio telephones

Philips Semiconductors
Low-voltage dual frequency
synthesizer for radio telephones
Product specification
UMA1020M
PINNING
SYMBOL PIN
DESCRIPTION
FAST
1 control input to speed-up main
synthesizer
CPPF
2 principal synthesizer speed-up
charge-pump output
CPP
3 principal synthesizer normal
charge-pump output
V_DD1
V_DD2
PRI
4 digital power supply 1
5 digital power supply 2
6 2 GHz principal synthesizer
frequency input
DGND
7 digital ground
f_XTAL
POFF
8 crystal frequency input from TCXO
9 principal synthesizer power-down
input
DOUT
10 7-bit digital-to-analog output
CLK
11 programming bus clock input
DATA
12 programming bus data input
E
13 programming bus enable input
(active LOW)
I_SET
14 regulator pin to set the charge-pump
currents
AUX
15 auxiliary synthesizer frequency input
AGND
16 analog ground
CPA
17 auxiliary synthesizer charge-pump
output
V_CC
18 supply for charge-pump and DAC
circuits
AOFF
19 auxiliary synthesizer power-down
input
LOCK
20 in-lock detect output (main PLL); test
mode output
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Principal synthesizer
Programmable reference and main dividers drive the
principal PLL phase detector. Two charge pumps produce
phase error current pulses for integration in an external
loop filter. A hardwired power-down input POFF (pin 9)
ensures that the dividers and phase comparator circuits
can be disabled.
The PRI input (pin 6) drives a preamplifier to provide the
clock to the first divider stage. The preamplifier has a high
input impedance, dominated by pin and pad capacitance.
The circuit operates with signal levels from 60 mV to
180 mV (RMS), and at frequencies up to 2.4 GHz. The
high frequency divider circuits use bipolar transistors,
slower bits are CMOS. Divide ratios (512 to 131071) allow
a 2 MHz phase comparison frequency.
1995 Jun 15
4