SAA7197 Datasheet, PDF(4/16 Page) NXP Semiconductors – Clock Generator Circuit for desktop video systems CGC

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SAA7197 Datasheet, PDF (4/16 Pages) NXP Semiconductors – Clock Generator Circuit for desktop video systems CGC

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Philips Semiconductors

Clock Generator Circuit for desktop video systems (CGC)

Product speciï¬cation

SAA7197

Source select LFCOSEL

Line frequency control signal LFCO (pin 11) is selected by

LFCOSEL = LOW. LFCOSEL = HIGH selects LFCO2

input signal (pin 19). This function is not tested.

Chip enable CE

The buffer outputs are enabled and RESN set HIGH by

CE = HIGH (Fig.4). CE = LOW sets the clock outputs

HIGH and RESN output LOW.

Power-on reset

Power-on reset is activated at power-on, when the supply

voltage decreases below 3.5 V (Fig.4) or when chip enable

is done. The indicator output RESN is LOW for a time

determined by capacitor on pin 3. The RESN signal can be

applied to reset other circuits of this digital TV system.

The LFCO or LFCO2 input signals have to be applied

before RESN becomes HIGH.

CREF output

2 fLFCO output to control the clock dividers of the

DMSD-SQP chip family.

PINNING

SYMBOL

PORD

VSSA

VDDA

VSSD1

LLCA

VDDD1

VSSD2

LLCB

LFCO

RESN

VSSD3

LLC2A

CREF

LFCOSEL

VDDD2

VSSD4

LFCO2

LLC2B

PIN DESCRIPTION

1 mode select input (LOW = PLL mode)(1)

2 chip enable /reset (HIGH = outputs enabled)

3 power-on reset delay, dependent on external

capacitor

4 analog ground (0 V)

5 analog supply voltage (+5 V)

6 digital ground 1 (0 V)

7 line-locked clock output signal (4 times fLFCO)

8 digital supply voltage 1 (+5 V)

9 digital ground 2 (0 V)

10 line-locked clock output signal (4 times fLFCO)

11 line-locked frequency control input signal 1

12 reset output (active-LOW, Fig.4)

13 digital ground 3 (0 V)

14 line-locked clock output signal 2A (2 times fLFCO)

15 clock reference output, qualiï¬er signal

(2 times fLFCO)

16 LFCO source select (LOW = LFCO selected)(1)

17 digital supply voltage 2 (+5 V)

18 digital ground 4 (0 V)

19 line-locked frequency control input signal 2(1)

20 line-locked clock output signal 2B (2 times fLFCO)

Note

1. MS and LFCO2 functions are not tested. LFCO2 is a multiple of

horizontal frequency.

PIN CONFIGURATION

halfpage

MS 1

20 LLC2B

CE 2

19 LFCO2

PORD 3

18 VSSD4

VSSA 4

17 VDDD2

VDDA 5

VSSD1 6

16 LFCOSEL

SAA7197

15 CREF

LLCA 7

14 LLC2A

VDDD1 8

13 VSSD3

VSSD2 9

12 RESIN

LLCB 10

11 LFCO

MGL505

Fig.2 Pin configuration.

August 1996

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