SAA7197 Datasheet, PDF (3/16 Pages) NXP Semiconductors – Clock Generator Circuit for desktop video systems CGC

Philips Semiconductors
Clock Generator Circuit for desktop video systems (CGC)
Product specification
SAA7197
BLOCK DIAGRAM
handbook, full pagewidth
MS 1
V_DDA V_DDD1 V_DDD2
5
8
17
SAA7197
LOOP
FILTER
VCO
MS = LOW
PHASE
DETECTOR
FREQUENCY
DIVIDER
1:2
FREQUENCY
DIVIDER
1:2
DELAY
LFCO 11
LFCO2 19
CE
2
PRE-FILTER
AND
PULSE
SHAPER
LFCOSEL
POWER-ON
RESET
16
3
PORD
4
V_SSA
6, 9, 13, 18
V_SSD
Fig.1 Block diagram.
7
LLCA
10
LLCB
14
LLC2A
20
LLC2B
15
CREF
12
RESN
MEH461
FUNCTION DESCRIPTION
The SAA7197 generates all clock signals required for a
digital TV system suitable for the SAA719x family
consisting of an 8-bit analog-to-digital converter (ADC8),
digital video multistandard decoder, square pixel
(DMSD-SQP), digital video colour space converter
(DCSC) and optional extensions. The SAA7197 completes
a system for Desktop Video applications in conjunction
with memory controllers.
The input signal LFCO is a digital-to-analog converted
signal provided by the DMDS-SQPs horizontal PLL. It is
the multiple of the line frequency:
7.38 MHz = 472 × f_H in 50 Hz systems
6.14 MHz = 360 × f_H in 60 Hz systems
LFCO2 (TTL-compatible signal from an external reference
source) can be applied to pin 19 (LFCOSEL = HIGH).
The input signal LFCO or LFCO2 is multiplied by factors 2
or 4 in the PLL (including phase detector, loop filter, VCO
and frequency divider) and output on LLCA (pin7), LLCB
(pin 10), LLC2A (pin 14) and LLC2B (pin 20). The
rectangular output signals have 50% duty factor. Outputs
with equal frequency may be connected together
externally. The clock outputs go HIGH during power-on
reset (and chip enable) to ensure that no output clock
signals are available the PLL has locked-on.
Mode select MS
The LFCO input signal is directly connected to the VCO at
MS = HIGH. The circuit operates as an oscillator and
frequency divider. This function is not tested.
August 1996
3