PHP50N06LT Datasheet, PDF (4/10 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP50N06LT, PHB50N06LT, PHD50N06LT
ID / A
1000
7524-55
RDS(ON) = VDS / ID
100
tp = 10 us
100 us
10
DC
1 ms
10 ms
100 ms
1
1
10
100
1000
VDS / V
Fig.3. Safe operating area. T_mb = 25 ˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
Transient thermal impedance, Zth (K/W)
10
1 _0.5
0.2
0.1
0.1 _0.05
0.02
0.01
0
P_D
tp
D
=
tp
T
T
t
0.001
10us
1ms
0.1s
10s
pulse width, tp (s)
Fig.4. Transient thermal impedance.
Z_{th j-mb} = f(t); parameter D = t_p/T
Drain current, ID (A)
100
10
6
8
80
VGS = 5.0 V
4.8
4.6
4.4
4.2
60
4.0
3.8
40
3.6
3.4
3.2
20
2.6
3.0
2.8
0
0
2 _{Drain-s4ource voltag6e, VDS (V)} 8
10
Fig.5. Typical output characteristics, T_j = 25 ˚C.
I_D = f(V_DS); parameter V_GS
40 ^RDS(ON)/mOhm
35
VGS/V =
30
25
4
4.2
4.4
4.6
4.8
5
20
15
10 15 20 25 30 35 40 45 50 55 60 65 70 75
ID/A
Fig.6. Typical on-state resistance, T_j = 25 ˚C.
R_DS(ON) = f(I_D); parameter V_GS
100
ID/A
80
60
40
20
Tj/C = 175
25
0
0
1
2
3
4
5
6
7
VGS/V
Fig.7. Typical transfer characteristics.
I_D = f(V_GS) ; conditions: V_DS = 25 V; parameter T_j
Transconductance, gfs (S)
40
35
30
25
20
15
10
50
20
40
60
80
100
Drain current, ID (A)
Fig.8. Typical transconductance, T_j = 25 ˚C.
g_fs = f(I_D); conditions: V_DS = 25 V
September 1998
4
Rev 1.400