PHP50N06LT Datasheet, PDF (1/10 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP50N06LT, PHB50N06LT, PHD50N06LT
FEATURES
SYMBOL
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
d
g
s
QUICK REFERENCE DATA
V_DSS = 55 V
I_D = 50 A
R_DS(ON) ≤ 24 mΩ (V_GS = 5 V)
R_DS(ON) ≤ 22 mΩ (V_GS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP50N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB50N06LT is supplied in the SOT404 surface mounting package.
The PHD50N06LT is supplied in the SOT428 surface mounting package.
PINNING
PIN DESCRIPTION
1 gate
SOT78 (TO220AB)
tab
SOT404
tab
SOT428
tab
2 drain¹
3 source
tab drain
1 23
2
13
2
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DSS
V_DGR
V_GS
I_D
I_DM
P_D
T_j, T_stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
T_j = 25 ˚C to 175˚C
T_j = 25 ˚C to 175˚C; R_GS = 20 kΩ
T_mb = 25 ˚C
T_mb = 100 ˚C
T_mb = 25 ˚C
T_mb = 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
± 13
50
35
200
125
175
UNIT
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.
September 1998
1
Rev 1.400