PHP50N06LT Datasheet, PDF (3/10 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP50N06LT, PHB50N06LT, PHD50N06LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T_j = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
I_S
Continuous source current
(body diode)
I_SM
Pulsed source current (body
diode)
V_SD
Diode forward voltage
I_F = 25 A; V_GS = 0 V
I_F = 40 A; V_GS = 0 V
t_rr
Reverse recovery time
I_F = 40 A; -dI_F/dt = 100 A/µs;
Q_rr
Reverse recovery charge V_GS = -10 V; V_R = 30 V
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
W_DSS
Drain-source non-repetitive I_D = 40 A; V_DD ≤ 25 V; V_GS = 5 V;
unclamped inductive turn-off R_GS = 50 Ω; T_mb = 25 ˚C
energy
MIN. TYP. MAX. UNIT
-
- 50 A
-
- 200 A
- 0.95 1.2 V
- 1.0 -
V
- 40 - ns
- 0.07 - µC
MIN.
-
MAX.
80
UNIT
mJ
120 ^PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
Fig.1. Normalised power dissipation.
PD% = 100⋅P_D/P_{D 25 ˚C} = f(T_mb)
ID%
120
Normalised Current Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
Fig.2. Normalised continuous drain current.
ID% = 100⋅I_D/I_{D 25 ˚C} = f(T_mb); conditions: V_GS ≥ 5 V
September 1998
3
Rev 1.400