BUJ100_15 Datasheet, PDF (4/10 Pages) NXP Semiconductors – Silicon Diffused Power Transistor

NXP Semiconductors
Silicon Diffused Power Transistor
+ 50v
100-200R
Horizontal
Oscilloscope
Vertical
300R
1R
6V
30-60 Hz
Fig.1. Test circuit for V_CEOsust.
IC / mA
250
100
10
0
Fig.2.
VCE / V
min
VCEOsust
Oscilloscope display for V_CEOsust.
120 ^PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.3. Normalised power dissipation.
PD% = 100⋅PD/PD _25˚C = f (T_mb)
Product specification
BUJ100
!
Zth / (K/W)
100
0.5
10 _0.2
0.1
0.05
1 _0.02
0.1
D=0
P_D
tp
D=
tp
T
T
t
0.01
1u 10u 100u 1m 10m 100m 1 10 100
t/s
Fig.4. Transient thermal impedance.
Zth _j-lead = f(t); parameter D = t_p/T
HFE
30
20
15
125 C
10
25 C
-40 C
VCE = 1V
5
1
0.001
Fig.5.
0.01
0.1
IC/A
1
23 5
Typical DC current gain. h_FE = f(I_C)
parameter V_CE
HFE
30
125 C
25 C
10
-40 C
VCE = 5V
1
0.001
Fig.6.
0.01
0.1
IC/A
1
23 5
Typical DC current gain. h_FE = f(I_C)
parameter V_CE
September 1999
3
Rev 1.000