83C748 Datasheet, PDF (4/18 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count

Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
Preliminary specification
83C748/87C748
PIN DESCRIPTIONS
MNEMONIC
V_SS
V_CC
P0.0–P0.2
PIN NO.
DIP/
SSOP
LCC
12
14
24
28
8–6 9–7
6
7
7
8
8
9
TYPE
NAME AND FUNCTION
I Circuit Ground Potential
I Supply voltage during normal, idle, and power-down operation.
I/O Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance inputs. These pins are driven low if the port register
bit is written with a 0. The state of the pin can always be read from the port register by the program.
P0.0 and P0.1 are open drain bidirectional I/O pins. While these differ from “standard TTL”
characteristics, they are close enough for the pins to still be used as general-purpose I/O. Port 0
also provides alternate functions for programming the EPROM memory as follows:
N/A V_PP (P0.2) – Programming voltage input. (See Note 1).
I OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
I ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
P1.0–P1.7
13–20 15–20, I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written
23, 24
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins
that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical
Characteristics: I_IL). Port 1 serves to output the addressed EPROM contents in the verify mode and
accepts as inputs the value to program into the selected address during the program mode. Port 1
also serves the special function features of the 80C51 family as listed below:
18
20
I INT0 (P1.5): External interrupt.
19
23
I INT1 (P1.6): External interrupt.
20
24
I T0 (P1.7): Timer 0 external input.
P3.0–P3.7
5–1, 6, 4–1, I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
23–21 27–25
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins
that are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: I_IL). Port 3 also functions as the address input for the EPROM memory location to be
programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL.
RST
X1
9
11
I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to V_SS permits a power-on RESET using only an external capacitor to
V_CC. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places
the device in the programming state allowing programming address, data and V_PP to be applied for
programming or verification purposes. The RESET serial sequence must be synchronized with the
X1 input.
11
13
I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
X2
10
12
O Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
1. When P0.2 is at or close to 0 volts, it may affect the internal ROM operation. It is recommended that P0.2 be tied to V_CC via a small pull-up
(e.g. 2kW).
ABSOLUTE MAXIMUM RATINGS^{1, 2}
PARAMETER
RATING
UNIT
Storage temperature range
–65 to +150
°C
Voltage from V_CC to V_SS
Voltage from any pin to V_SS (except V_PP)
Power dissipation
–0.5 to +6.5
V
–0.5 to V_CC + 0.5
V
1.0
W
Voltage on V_PP pin to V_SS
0 to +13.0
V
Maximum I_OL per I/O pin
10
mA
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
1999 Apr 15
4