83C748 Datasheet, PDF (12/18 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count

Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
Preliminary specification
83C748/87C748
Security Bits
Two security bits, security bit 1 and security bit 2, are provided to
limit access to the USER EPROM and encryption key arrays.
Security bit 1 is the program inhibit bit, and once programmed
performs the following functions:
1. Additional programming of the USER EPROM is inhibited.
2. Additional programming of the encryption key is inhibited.
3. Verification of the encryption key is inhibited.
4. Verification of the USER EPROM and the security bit levels may
still be performed.
(If the encryption key array is being used, this security bit should be
programmed by the user to prevent unauthorized parties from
reprogramming the encryption key to all logical zero bits. Such
programming would provide data during a verify cycle that is the
logical complement of the USER EPROM contents).
Security bit 2, the verify inhibit bit, prevents verification of both the
USER EPROM array and the encryption key arrays. The security bit
levels may still be verified.
Programming and Verifying Security Bits
Security bits are programmed employing the same techniques used
to program the USER EPROM and KEY arrays using serial data
streams and logic levels on port pins indicated in Table 3. When
programming either security bit, it is not necessary to provide
address or data information to the 87C748 on ports 1 and 3.
Verification occurs in a similar manner using the RESET serial
stream shown in Table 3. Port 3 is not required to be driven and the
results of the verify operation will appear on ports 1.6 and 1.7.
Ports 1.7 contains the security bit 1 data and is a logical one if
programmed and a logical zero if not programmed. Likewise, P1.6
contains the security bit 2 data and is a logical one if programmed
and a logical zero if not programmed.
EPROM PROGRAMMING AND VERIFICATION
T_amb = 21°C to +27°C, V_CC = 5V ±10%, V_SS = 0V
SYMBOL
PARAMETER
MIN
1/t_CLCL
Oscillator/clock frequency
1.2
t_AVGL1
Address setup to P0.1 (PROG–) low
10µs + 24t_CLCL
t_GHAX
Address hold after P0.1 (PROG–) high
48t_CLCL
t_DVGL
Data setup to P0.1 (PROG–) low
38t_CLCL
t_GHDX
Data hold after P0.1 (PROG–) high
36t_CLCL
t_SHGL
V_PP setup to P0.1 (PROG–) low
10
t_GHSL
V_PP hold after P0.1 (PROG–)
10
t_GLGH
P0.1 (PROG–) width
90
t_AVQV2
V_PP low (V_CC) to data valid
t_GHGL
P0.1 (PROG–) high to P0.1 (PROG–) low
10
t_MASEL
ASEL high time
13t_CLCL
t_HAHLD
Address hold time
2t_CLCL
t_HASET
Address setup to ASEL
13t_CLCL
t_ADSTA
Low address to valid data
NOTES:
1. Address should be valid at least 24t_CLCL before the rising edge of P0.2 (V_PP).
2. For a pure verify mode, i.e., no program mode in between, t_AVQV is 14t_CLCL maximum.
MAX
6
110
48t_CLCL
48t_CLCL
UNIT
MHz
µs
µs
µs
µs
1999 Apr 15
12