83C748 Datasheet, PDF (10/18 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count

Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
Preliminary specification
83C748/87C748
TCON Register
MSB
LSB
GATE C/T
TF
TR
IE0
IT0
IE1
IT1
GATE
C/T
TF
TR
IE0
IT0
IE1
IT1
1 – Timer/counter is enabled only when INT0 pin is high,
and TR is 1.
0 – Timer/counter is enabled when TR is 1.
1 – Counter/timer operation from T0 pin.
0 – Timer operation from internal clock.
1 – Set on overflow of TH.
0 – Cleared when processor vectors to interrupt routine
and by reset.
1 – Timer/counter enabled.
0 – Timer/counter disabled.
1 – Edge detected in INT0.
1 – INT0 is edge triggered.
0 – INT0 is level sensitive.
1 – Edge detected on INT1.
1 – INT1 is edge triggered.
0 – INT1 is level sensitive.
These flags are functionally identical to the corresponding 80C51
flags, except that there is only one timer on the 83C748 and the
flags are therefore combined into one register.
Note that the positions of the IE0/IT0 and IE1/IT1 bits are transposed
from the positions used in the standard 80C51 TCON register.
Timer I Implementation
Timer I is clocked once per machine cycle, which is the oscillator
frequency divided by 12. The timer operation is enabled by setting
the TIRUN bit (bit 4) in the I2CFG register. Writing a 0 into the
TIRUN bit will stop and clear the timer. The timer is 10 bits wide, and
when it reaches the terminal count of 1024, it carries out and sets
the Timer I interrupt flag. An interrupt will occur if the Timer I
interrupt is enabled by bit ETI (bit 4) of the Interrupt Enable (IE)
register, and global interrupts are enabled by bit EA (bit 7) of the
same IE register.
The vector address for the Timer I interrupt is 1Bhex, and the
interrupt service routine must start at this address. As with all 8051
family microcontrollers, only the Program Counter is pushed onto
the stack upon interrupt (other registers that are used both by the
interrupt service routine and elsewhere must be explicitly saved).
The Timer I interrupt flag is cleared by setting the CKRTI bit (bit 5 of
the I1CFG register. For more information, see application note
AN427.
Interrupts
The interrupt structure is a four-source, one-level interrupt system.
Interrupt sources common to the 80C51 are the external interrupts
(INT0, INT1) and the timer/counter interrupt (ET0). Timer I interrupt
(ETI) is the other interrupt source. The interrupt sources are listed
below in their order of polling sequence priority.
Upon interrupt or reset the program counter is loaded with specific
values for the appropriate interrupt service routine in program
memory. These values are:
Program Memory
Event
Address
Reset
000
INT0
003
Counter/Timer 0
00B
INT1
013
Timer I
01B
Priority
Highest
Lowest
The interrupt enable register (IE) is used to individually enable or
disable the four sources. Bit EA in the interrupt enable register can
be used to globally enable or disable all interrupt sources. The
interrupt enable register is described below. All other interrupt details
are based on the 80C51 interrupt architecture.
Interrupt Enable Register
EA
X
X
—
ETI
EX1
ET0
EX0
Symbol Position
EA
IE.7
–
IE.6
–
IE.5
–
IE.4
ETI
IE.3
EX1
IE.2
ET0
IE.1
EX0
IE.0
Function
Disables all interrupts. If EA = 0, no interrupt
will be acknowledged. If EA = 1, each
interrupt source is individually enabled or
disabled by setting or clearing its enable bit
Reserved
Reserved
Reserved
Enables or disables the Timer I overflow
interrupt. If ET1 = 0, the Timer I interrupt is
disabled.
Enables or disables external interrupt 1.
If EX1 = 0, external interrupt 1 is disabled.
Enables or disables the Timer 0 overflow
interrupt. If ET0 = 0, theTimer 0 interrupt is
disabled.
Enables or disables external interrupt 0.
If EX0 = 0, external interrupt 0 is disabled.
OSC
T0 Pin
TR
Gate
INT0 Pin
1999 Apr 15
÷ 12
C/T = 0
C/T = 1
TL
TH
TF
Reload
RTL
RTH
Figure 4. 83C748 Counter/Timer Block Diagram
10
Int.
SU00300