80C31X2 Datasheet, PDF (39/62 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/8K/16K/32K ROM/OTP 128B/256B RAM low voltage 2.7 to 5.5 V, low power, high speed 30/33 MHz

Philips Semiconductors
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
DC ELECTRICAL CHARACTERISTICS
T_amb = 0 °C to +70 °C or –40 °C to +85 °C; V_CC = 5 V ±10%; V_SS = 0 V (30/33 MHz max. CPU clock)
SYMBOL PARAMETER
TEST
CONDITIONS
LIMITS
MIN
V_IL
V_IH
V_IH1
V_OL
V_OL1
V_OH
V_OH1
Input low voltage¹¹
Input high voltage (ports 0, 1, 2, 3, EA)
Input high voltage, XTAL1, RST¹¹
Output low voltage, ports 1, 2, 3 ⁸
Output low voltage, port 0, ALE, PSEN ^{7, 8}
Output high voltage, ports 1, 2, 3 ³
Output high voltage (port 0 in external bus
mode), ALE⁹, PSEN³
4.5 V < V_CC < 5.5 V
–
–
V_CC = 4.5 V; I_OL = 1.6 mA²
V_CC = 4.5 V; I_OL = 3.2 mA²
V_CC = 4.5 V; I_OH = –30 mA
V_CC = 4.5 V; I_OH = –3.2 mA
–0.5
0.2 V_CC+0.9
0.7 V_CC
–
–
V_CC – 0.7
V_CC – 0.7
I_IL
Logical 0 input current, ports 1, 2, 3
V_IN = 0.4 V
–1
I_TL
Logical 1-to-0 transition current, ports 1, 2, 3⁶ V_IN = 2.0 V; See note 4
–
I_LI
Input leakage current, port 0
0.45 < V_IN < V_CC – 0.3
–
I_CC
Power supply current (see Figure 34):
Active mode (see Note 5)
TYP¹
MAX
0.2 V_CC–0.1
V_CC+0.5
V_CC+0.5
0.4
0.4
–
–
–50
–650
±10
UNIT
V
V
V
V
V
V
V
mA
mA
mA
V_RAM
R_RST
C_IO
Idle mode (see Note 5)
Power-down mode or clock stopped
(see Figure 39 for conditions)
RAM keep-alive voltage
Internal reset pull-down resistor
Pin capacitance¹⁰ (except EA)
T_amb = 0 °C to 70 °C
T_amb = –40 °C to +85 °C
–
1.2
–
40
–
–
2
30
mA
3
50
mA
V
225
kΩ
15
pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V_OLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I_OL can exceed these conditions provided that no
single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V_OH on ALE and PSEN to momentarily fall below the V_CC–0.7 specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V_IN is approximately 2 V.
5. See Figures 36 through 39 for I_CC test conditions and Figure 34 for I_CC vs. Frequency.
12-clock mode characteristics:
Active mode (operating): I_CC(MAX) = 1.0 mA + 0.9 mA × FREQ.[MHz]
Active mode (reset):
I_CC(MAX) = 7.0 mA + 0.5 mA x FREQ.[MHz]
Idle mode:
I_CC(MAX) = 1.0 mA + 0.18 mA × FREQ.[MHz]
6. This value applies to T_amb = 0°C to +70°C. For T_amb = –40°C to +85°C, I_TL = –750 µΑ.
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, I_OL must be externally limited as follows:
Maximum I_OL per port pin:
15 mA (*NOTE: This is 85 °C specification.)
Maximum I_OL per 8-bit port:
26 mA
Maximum total I_OL for all outputs: 71 mA
If I_OL exceeds the test condition, V_OL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. ALE is tested to V_OH1, except when ALE is off then V_OH is the voltage specification.
10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
(except EA is 25 pF).
11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection
circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection.
2003 Jan 24
39