80C31X2 Datasheet, PDF (36/62 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/8K/16K/32K ROM/OTP 128B/256B RAM low voltage 2.7 to 5.5 V, low power, high speed 30/33 MHz

Philips Semiconductors
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
Table 8. Interrupt Table
SOURCE
POLLING PRIORITY
External interrupt 0
1
Timer 0
2
External interrupt 1
3
Timer 1
4
UART
5
Timer 2
6
NOTES:
1. L = Level activated
2. T = Transition activated
REQUEST BITS
IE0
TF0
IE1
TF1
RI, TI
TF2, EXF2
HARDWARE CLEAR?
N (L)¹ Y (T)²
Y
N (L) Y (T)
Y
N
N
VECTOR ADDRESS
03H
0BH
13H
1BH
23H
2BH
Reduced EMI
All port pins have slew rate controlled outputs. This is to limit noise
generated by quickly switching output signals. The slew rate is
factory set to approximately 10 ns rise and fall times.
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.
AUXR (8EH)
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
AO
AUXR.0
AO
Turns off ALE output.
Dual DPTR
The dual DPTR structure (see Figure 26) enables a way to specify
the address of an external data memory location. There are two
16-bit DPTR registers that address the external memory, and a
single bit called DPS = AUXR1/bit0 that allows the program code to
switch between them.
• New Register Name: AUXR1#
• SFR Address: A2H
• Reset Value: xxx000x0B
AUXR1 (A2H)
7
6
5
4
3
2
1
0
–
–
–
LPEP WUPD
0
–
DPS
Where:
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
Select Reg
DPTR0
DPTR1
DPS
0
1
Note that bit 2 is not writable and is always read as a zero. This
allows the DPS bit to be quickly toggled simply by executing an INC
DPTR instruction without affecting the WUPD or LPEP bits.
DPS
BIT0
AUXR1
DPH
(83H)
DPL
(82H)
DPTR1
DPTR0
Figure 26.
EXTERNAL
DATA
MEMORY
SU00745A
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
INC DPTR
Increments the data pointer by 1
MOV DPTR, #data16 Loads the DPTR with a 16-bit constant
MOV A, @ A+DPTR Move code byte relative to DPTR to ACC
MOVX A, @ DPTR
Move external RAM (16-bit address) to
ACC
MOVX @ DPTR , A
Move ACC to external RAM (16-bit
address)
JMP @ A + DPTR
Jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
2003 Jan 24
36