80C31X2 Datasheet, PDF (12/62 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/8K/16K/32K ROM/OTP 128B/256B RAM low voltage 2.7 to 5.5 V, low power, high speed 30/33 MHz

Philips Semiconductors
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
Table 1.
SYMBOL
ACC*
AUXR#
AUXR1#
B*
CKCON
DPTR:
DPH
DPL
IE*
IP*
IPH#
P0*
P1*
P2*
P3*
Special Function Registers
DESCRIPTION
DIRECT
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
ADDRESS _MSB
LSB
Accumulator
E0H
E7
E6
E5
E4
E3
E2
E1
E0
Auxiliary
Auxiliary 1
8EH
–
–
–
–
–
–
–
AO
A2H
–
–
–
LPEP² WUPD
0
–
DPS
B register
F0H
F7
F6
F5
F4
F3
F2
F1
F0
Clock Control Register 8FH
–
–
–
–
–
–
–
X2
Data Pointer (2 bytes)
Data Pointer High
83H
Data Pointer Low
82H
AF
AE
AD
AC
AB
AA
A9
A8
Interrupt Enable
A8H
EA
–
ET2
ES
ET1 EX1 ET0 EX0
BF
BE
BD
BC
BB
BA
B9
B8
Interrupt Priority
B8H
–
–
PT2
PS
PT1 PX1 PT0 PX0
Interrupt Priority High
B7H
–
–
PT2H PSH PT1H PX1H PT0H PX0H
87
86
85
84
83
82
81
80
Port 0
80H
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
97
96
95
94
93
92
91
90
Port 1
90H
–
–
–
–
–
– T2EX T2
A7
A6
A5
A4
A3
A2
A1
A0
Port 2
A0H AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8
B7
B6
B5
B4
B3
B2
B1
B0
Port 3
B0H
RD
WR
T1
T0
INT1 INT0 TxD RxD
RESET
VALUE
00H
xxxxxxx0B
xxx000x0B
00H
xxx00000B
00H
00H
0x000000B
xx000000B
xx000000B
FFH
FFH
FFH
FFH
PCON#¹ Power Control
87H SMOD1 SMOD0
–
POF GF1 GF0 PD
IDL
D7
D6
D5
D4
D3
D2
D1
D0
PSW*
Program Status Word
D0H
CY
AC
F0
RS1
RS0
OV
–
P
RACAP2H# Timer 2 Capture High
RACAP2L# Timer 2 Capture Low
CBH
CAH
SADDR# Slave Address
A9H
SADEN# Slave Address Mask
B9H
SBUF
Serial Data Buffer
99H
9F
9E
9D
9C
9B
9A
99
98
SCON*
Serial Control
98H SM0/FE SM1 SM2 REN
TB8
RB8
TI
RI
SP
Stack Pointer
81H
8F
8E
8D
8C
8B
8A
89
88
TCON*
Timer Control
88H
TF1
TR1
TF0
TR0
IE1
IT1 IE0
IT0
CF
CE
CD
CC
CB
CA
C9
C8
T2CON* Timer 2 Control
C8H
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
T2MOD# Timer 2 Mode Control
C9H
–
–
–
–
–
– T2OE DCEN
TH0
Timer High 0
8CH
TH1
Timer High 1
8DH
TH2#
Timer High 2
CDH
TL0
Timer Low 0
8AH
TL1
Timer Low 1
8BH
TL2#
Timer Low 2
CCH
TMOD
Timer Mode
89H GATE C/T
M1
M0 GATE C/T M1
M0
NOTE:
Unused register bits that are not defined should not be set by the user’s program. If violated, the device could function incorrectly.
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
– Reserved bits.
1. Reset value depends on reset source.
2. LPEP – Low Power EPROM operation (OTP only)
00xx0000B
000000x0B
00H
00H
00H
00H
xxxxxxxxB
00H
07H
00H
00H
xxxxxx00B
00H
00H
00H
00H
00H
00H
00H
2003 Jan 24
12