LPC1768 Datasheet, PDF (35/72 Pages) NXP Semiconductors – 32-bit ARM Cortex-M3 microcontroller up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN

NXP Semiconductors
LPC1768/66/65/64
32-bit ARM Cortex-M3 microcontroller
V_DD(3V3)
V_SS
V_DD(REG)(3V3)
LPC17xx
to I/O pads
3.3 V REGULATOR
MAIN POWER DOMAIN
to core
to memories,
peripherals,
oscillators,
PLLs
VBAT
RTCX1
RTCX2
V_DDA
VREFP
VREFN
V_SSA
POWER
SELECTOR
32 kHz
OSCILLATOR
ULTRA-LOW
POWER
REGULATOR
BACKUP REGISTERS
REAL-TIME CLOCK
RTC POWER DOMAIN
DAC
ADC
ADC POWER DOMAIN
Fig 5. Power distribution
002aad978
7.30 System control
7.30.1 Reset
Reset has four sources on the LPC1768/66/65/64: the RESET pin, the Watchdog reset,
power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a
Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating
voltage attains a usable level, starts the Wake-up timer (see description in
Section 7.29.5), causing reset to remain asserted until the external Reset is de-asserted,
the oscillator is running, a fixed number of clocks have passed, and the flash controller
has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
LPC1768_66_65_64_2
Objective data sheet
Rev. 02 — 11 February 2009
© NXP B.V. 2009. All rights reserved.
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