LPC1768 Datasheet, PDF (1/72 Pages) NXP Semiconductors – 32-bit ARM Cortex-M3 microcontroller up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN

LPC1768/66/65/64
32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and
64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
Rev. 02 — 11 February 2009
Objective data sheet
1. General description
The LPC1768/66/65/64 are ARM Cortex-M3 based microcontrollers for embedded
applications featuring a high level of integration and low power consumption. The ARM
Cortex-M3 is a next generation core that offers system enhancements such as enhanced
debug features and a higher level of support block integration.
The LPC1768/66/65/64 operate at CPU frequencies of up to 100 MHz. The ARM
Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals. The ARM
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branching.
The peripheral complement of the LPC1768/66/65/64 includes up to 512 kB of flash
memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface,
8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers,
SPI interface, 3 I²C-bus interfaces, 2-input plus 2-output I²S-bus interface, 8-channel
12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general
purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC)
with separate battery supply, and up to 70 general purpose I/O pins.
The LPC1768/66/65/64 are pin-compatible to the 100-pin LPC236x ARM7-based
microcontroller series.
2. Features
I ARM Cortex-M3 processor, running at frequencies of up to 100 MHz. A Memory
Protection Unit (MPU) supporting eight regions is included.
I ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
I Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator
enables high-speed 100 MHz operation with zero wait states.
I In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
I On-chip SRAM includes:
N 32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU
access.
N Two/one 16 kB SRAM blocks with separate access paths for higher throughput.
These SRAM blocks may be used for Ethernet (LPC1768/66/64 only), USB, and
DMA memory, as well as for general purpose CPU instruction and data storage.