ISP1761BEUM Datasheet, PDF (32/164 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus On-The-Go controller

NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
The internal POR pulse will be generated whenever V_CC(5V0) drops below V_TRIP for more
than 11 µs.
V_CC(5V0)
V_TRIP
t0
t1
t_PORP
t2
t3
t4 t5
t_PORP
PORP⁽¹⁾
004aaa584
(1) PORP = Power-On Reset Pulse.
Fig 11. Internal power-on reset timing
The recommended RESET input pulse length at power-on must be at least 2 ms to ensure
that internal clocks are stable.
The RESET_N pin can be either connected to V_CC(I/O), using the internal POR circuit or
externally controlled by the microcontroller, ASIC, and so on. Figure 12 shows the
availability of the clock with respect to the external POR.
RESET_N
EXTERNAL CLOCK
004aaa583
A
Stable external clock is available at A.
Fig 12. Clock with respect to the external power-on reset
ISP1761_5
Product data sheet
Rev. 05 — 13 March 2008
© NXP B.V. 2008. All rights reserved.
31 of 163