ISP1761BEUM Datasheet, PDF (109/164 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus On-The-Go controller

NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.5.5 DcInterruptEnable register
This register enables or disables individual interrupt sources. The interrupt for each
endpoint can individually be controlled through the associated IEPnRX or IEPnTX bits,
here n represents the endpoint number. All interrupts can globally be disabled through
bit GLINTENA in the Mode register (see Table 100).
An interrupt is generated when the USB SIE receives or generates an ACK or NAK on the
USB bus. The interrupt generation depends on Debug mode settings of bit fields
CDBGMOD[1:0], DDBGMODIN[1:0] and DDBGMODOUT[1:0].
All data IN transactions use the Transmit buffers (TX) that are handled by DDBGMODIN
bits. All data OUT transactions go through the Receive buffers (RX) that are handled by
DDBGMODOUT bits. Transactions on control endpoint 0 (IN, OUT and SETUP) are
handled by CDBGMOD bits.
Interrupts caused by events on the USB bus (SOF, suspend, resume, bus reset, set up
and high-speed status) can also be individually controlled. A bus reset disables all
enabled interrupts, except bit IEBRST (bus reset) that remains unchanged.
The DcInterruptEnable register consists of 4 bytes. The bit allocation is given in Table 107.
Table 107. DcInterruptEnable - Device Controller Interrupt Enable register (address 0214h) bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved^[1]
IEP7TX
IEP7RX
Reset
0
0
0
0
0
0
0
0
Bus reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
IEP6TX IEP6RX
IEP5TX
IEP5RX
IEP4TX
IEP4RX IEP3TX
IEP3RX
Reset
0
0
0
0
0
0
0
0
Bus reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
IEP2TX IEP2RX
IEP1TX
IEP1RX
IEP0TX IEP0RX reserved^[1] IEP0SETUP
Reset
0
0
0
0
0
0
0
0
Bus reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
IEVBUS IEDMA IEHS_STA IERESM IESUSP IEPSOF IESOF
IEBRST
Reset
0
0
0
0
0
0
0
0
Bus reset
0
0
0
0
0
0
0
unchanged
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[1] The reserved bits should always be written with the reset value.
ISP1761_5
Product data sheet
Rev. 05 — 13 March 2008
© NXP B.V. 2008. All rights reserved.
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