UJA1065 Datasheet, PDF (30/67 Pages) NXP Semiconductors – High-speed CAN/LIN fail-safe system basis chip

Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Table 6:
Bit
11 to 6
Mode register bit description (bits 11 to 6) ^[1]
Symbol
Description
Value
Time
Normal
mode (ms)
NWP[5:0] Nominal
00 1001
4
Watchdog Period _{00 1100}
8
WDPRE = 00 (as
set in the Special
01 0010
16
Mode register) ^{01 0100}
32
01 1011
40
10 0100
48
10 1101
56
11 0011
64
11 0101
72
11 0110
80
Nominal
00 1001
6
Watchdog Period _{00 1100}
12
WDPRE = 01 (as
set in the Special
01 0010
24
Mode register) ^{01 0100}
48
01 1011
60
10 0100
72
10 1101
84
11 0011
96
11 0101
108
11 0110
120
Nominal
00 1001
10
Watchdog Period _{00 1100}
20
WDPRE = 10 (as _{01 0010}
40
set in the Special
Mode register) ^{01 0100}
80
01 1011
100
10 0100
120
10 1101
140
11 0011
160
11 0101
180
11 0110
200
Standby
mode (ms)
20
40
80
160
320
640
1024
2048
4096
OFF ^[2]
30
60
120
240
480
960
1536
3072
6144
OFF ^[2]
50
100
200
400
800
1600
1560
5120
10240
OFF ^[2]
Flash mode
(ms)
20
40
80
160
320
640
1024
2048
4096
8192
30
60
120
240
480
960
1536
3072
6144
12288
50
100
200
400
800
1600
1560
5120
10240
20480
Sleep mode
(ms)
160
320
640
1024
2048
3072
4096
6144
8192
OFF ^[3]
240
480
960
1536
3072
4608
6144
9216
12288
OFF ^[3]
400
800
1600
2560
5120
7680
10240
15360
20480
OFF ^[3]
9397 750 14409
Objective data sheet
Rev. 01 — 10 August 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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