UJA1065 Datasheet, PDF (1/67 Pages) NXP Semiconductors – High-speed CAN/LIN fail-safe system basis chip

UJA1065
High-speed CAN/LIN fail-safe system basis chip
Rev. 01 — 10 August 2005
Objective data sheet
1. General description
The UJA1065 System Basis Chip (SBC) replaces basic discrete components which are
common in every Electronic Control Unit (ECU) with a Controller Area Network (CAN) and
a Local Interconnect Network (LIN) interface. The SBC supports all networking
applications which control various power and sensor peripherals by using high-speed
CAN as the main network interface and LIN as a local sub-bus. The SBC contains the
following integrated devices:
• High-speed CAN transceiver, inter-operable and downwards compatible with CAN
transceiver TJA1041 and TJA1041A, and compatible with the ISO11898-2 standard
and the ISO11898-5 standard (in preparation)
• LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3
• Advanced independant watchdog
• Dedicated voltage regulators for microcontroller and CAN transceiver
• Serial peripheral interface (full duplex)
• Local wake-up input port
• Inhibit / limp home output port
In addition to the advantages of integrating these common ECU functions in a single
package, the SBC offers an intelligent combination of system-specific functions such as:
• Advanced low power concept
• Safe and controlled system start-up behavior
• Advanced fail-safe system behavior that prevents any conceivable deadlock
• Detailed status reporting on system and sub-system levels
The UJA1065 is designed to be used in combination with a microcontroller with a CAN
controller. The SBC ensures that the microcontroller is always started up in a defined
manner. In failure situations the SBC will maintain the microcontroller function for as long
as possible, to provide full monitoring and software driven fall-back operation.
The UJA1065 is designed for 14 V single power supply architectures and for 14 V and
42 V dual power supply architectures.