SC16C752B Datasheet, PDF (30/47 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Philips Semiconductors
SC16C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.14 FIFO ready register
The FIFO ready register provides real-time status of the transmit and receive FIFOs
of both channels.
Table 22: FIFO Ready Register bits description
Bit Symbol
Description
7:6 FIFO Rdy[7:6] Unused; always 0.
5
FIFO Rdy[5]
RX FIFO B status. Related to DMA.
4
FIFO Rdy[4]
RX FIFO A status. Related to DMA.
3:2 FIFO Rdy[3:2] Unused; always 0.
1
FIFO Rdy[1]
TX FIFO B status. Related to DMA.
0
FIFO Rdy[0]
TX FIFO A status. Related to DMA.
The FIFO Rdy register is a read-only register that can be accessed when any of the
two UARTs is selected CSA or CSB = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and
loop-back is disabled. The address is 111.
9397 750 14443
Product data
Rev. 03 — 14 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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