SC16C752B Datasheet, PDF (1/47 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

SC16C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with
64-byte FIFOs
Rev. 03 — 14 December 2004
Product data
1. Description
The SC16C752B is a dual universal asynchronous receiver/transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to
5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a
transmission control register (TCR) that stores receiver FIFO threshold levels to
start/stop transmission during hardware and software flow control. With the FIFO
RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one
access. On-chip status registers provide the user with error indications, operational
status, and modem interface control. System interrupts may be tailored to meet user
requirements. An internal loop-back capability allows on-board diagnostics.
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and
receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or
8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be
programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can
transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect
break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can
detect FIFO underflow. The UART also contains a software interface for modem
control operations, and has software flow control and hardware flow control
capabilities.
The SC16C752B is available in plastic LQFP48 and HVQFN32 packages.
2. Features
s Dual channel
s Pin compatible with SC16C2550 with additional enhancements
s Up to 5 Mbit/s baud rate (at 3.3 V and 5 V; at 2.5 V maximum baud rate is
3 Mbit/s)
s 64-byte transmit FIFO
s 64-byte receive FIFO with error flags
s Programmable and selectable transmit and receive FIFO trigger levels for DMA
and interrupt generation
s Software/hardware flow control
x Programmable Xon/Xoff characters
x Programmable auto-RTS and auto-CTS
s Optional data flow resume by Xon any character
s DMA signalling capability for both received and transmitted data
s Supports 5 V, 3.3 V and 2.5 V operation
s 5 V tolerant inputs