TDA8703 Datasheet, PDF (3/18 Pages) NXP Semiconductors – 8-bit high-speed analog-to-digital converter

Philips Semiconductors
8-bit high-speed analog-to-digital converter
Product specification
TDA8703
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V_CCA
V_CCD
V_CCO
I_CCA
I_CCD
I_CCO
ILE
DLE
AILE
B
f_CLK/f_CLK
P_tot
analog supply voltage
digital supply voltage
output stages supply voltage
analog supply current
digital supply current
output stages supply current
DC integral linearity error
DC differential linearity error
AC integral linearity error
−3 dB bandwidth
maximum conversion rate
total power dissipation
note 1
note 2; f_CLK = 40 MHz
note 3
4.5
5.0
5.5
V
4.5
5.0
5.5
V
4.2
5.0
5.5
V
−
28
36
mA
−
19
25
mA
−
11
14
mA
−
−
±1
LSB
−
−
±1/2 LSB
−
−
±2
LSB
−
19.5 −
MHz
40
−
−
MHz
−
290
415
mW
Notes
1. Full-scale sinewave (f_i = 4.4 MHz; f_CLK; f_CLK = 27 MHz).
2. The −3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at input).
3. The circuit has two clock inputs CLK and CLK. There are four modes of operation:
a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the LOW-to-HIGH transition of the input clock signal.
b) TTL (mode 2); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the HIGH-to-LOW transition of the input clock signal.
c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.
d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.
1996 Aug 26
3