PDIUSBP11A Datasheet, PDF (3/12 Pages) NXP Semiconductors – Universal Serial Bus Transceiver

Philips Semiconductors
Universal Serial Bus transceiver
Product specification
PDIUSBP11A
PIN DESCRIPTION
PIN
PIN
No.
SYMBOL
3
RCV
2
OE#
1
MODE
12, 13
V_PO, V_MO/F_SEO
4, 5
V_P, V_M
11, 10
6
9
14
7
D+, D–
SUSPND
SPEED
V_CC
GND
I/O
O
I
I
I
O
AI/O
I
I
NAME AND FUNCTION
Receive data. CMOS level output for USB differential input
Output Enable. Active LOW, enables the transceiver to transmit data on the bus.
When not active the transceiver is in receive mode
Mode. When left unconnected, a weak pull-up transistor pulls it to V_CC and in this
mode, the PDIUSBP11A is backward compatible to PDIUSBP11. When connected to
GND, the VMO/FSEO pin takes the function of FSEO (Force SEO).
Inputs to differential driver. (Outputs from SIE).
MODE
VPO
VMO/FSEO RESULT
0
0
0
Logic “0”
0
1
SE0#
1
0
Logic “1”
1
1
SEO#
1
0
0
SE0#
0
1
Logic “0”
1
0
Logic “1”
1
1
Illegal code
Gated version of D– and D+. Outputs are logic “0” and logic “1”. Used to detect single
ended zero (SE0#), error conditions, and interconnect speed. (Inputs to SIE).
VP
VM
RESULT
0
0
SE0#
0
1
Low Speed
1
0
Full Speed
1
1
Error
Data+, Data–. Differential data bus conforming to the Universal Serial Bus standard.
Suspend. Enables a low power state while the USB bus is inactive. While the suspnd
pin is active it will drive the RCV pin to a logic “0” state. Both D+ and D– are tri-stated.
Edge rate control. Logic “1” operates at edge rates for “full speed”. Logic “0” operates
edge rates for “low speed”.
3.0V to 3.6V power supply
Ground reference
1999 Jun 04
3