74F564 Datasheet, PDF (3/10 Pages) NXP Semiconductors – Octal D flip-flop 3-State

Philips Semiconductors
Octal D flip-flop (3-State)
Product specification
74F564
LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
CP ¹¹
1
OE
V_CC=Pin 20
GND=Pin 10
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
SF01055
FUNCTION TABLE
INPUTS
OE
CP
Dn
INTERNAL
REGISTER
OUTPUTS
Q0 – Q7
L
↑
l
L
H
L
↑
h
H
L
L
↑
X
NC
NC
H
↑
X
NC
Z
H
↑
Dn
Dn
Z
H = High voltage level
h = High voltage level one setup time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to the Low-to-High clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low-to-High clock transition
↑ = Not a Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
V_CC
V_IN
I_IN
V_OUT
I_OUT
T_amb
T_stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature
OPERATING MODES
Load and read register
Hold
Disable outputs
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5.0
–0.5 to +V_CC
48
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
1996 Jan 05
3