74F564 Datasheet, PDF (2/10 Pages) NXP Semiconductors – Octal D flip-flop 3-State

Philips Semiconductors
Octal D flip-flop (3-State)
Product specification
74F564
FEATURES
• 74F564 is broadside pinout version of 74F534
• Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
• Useful as an Input or Ouput port for Microprocessors
• 3-State Ouputs for Bus interfacing
• Common Output Enable
• 74F574 is a non-inverting version of 74F564
DESCRIPTION
The 74F564 has a broadside pinout configuration to facilitate PC
board layout and allows easy interface with microprocessors.
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by the clock (CP) and Output Enable (OE) control gates.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independently of the register operation. When OE is Low, data in the
register appears at the outputs. When OE is High, the outputs are in
high impedance “off” state, which means they will neither drive nor
load the bus.
PIN CONFIGURATION
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 ⁹
GND 10
20 V_CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 _CP
SF01052
TYPE
74F564
TYPICAL f_MAX
180MHz
TYPICAL SUPPLY
CURRENT
(TOTAL)
50mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V_CC = 5V ±10%,
T_amb = 0°C to +70°C
20-Pin Plastic DIP
N74F564N
20-Pin Plastic SOL
N74F564D
PKG.
DWG #
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
D0 - D7
Data inputs
1.0/1.0
OE
Output Enable input (active Low)
1.0/1.0
CP
Clock Pulse input (active rising edge)
1.0/1.0
Q0 - Q7
3-State outputs
150/40
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
2
3
4
5
6
7
8
9
D0 D1 D2 D3 D4 D5 D6 D7
11
CP
1
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
V_CC=Pin 20
GND=Pin 10
19 18 17 16 15 14 13 12
SF01053
1
EN1
11
C2
2
2D
1
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
SF01054
1996 Jan 05
2
853-0166 16189