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| PCD6001 Datasheet, PDF (29/96 Pages) NXP Semiconductors – Digital telephone answering machine chip | |||
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Philips Semiconductors
Digital telephone answering machine chip
Product speciï¬cation
PCD6001
10.4.3 INTERRUPT ENABLE REGISTER 0 (IEN0)
Table 17 Interrupt Enable Register 0 (SFR address A8H); reset state 00H
7
global
enable
6
enable
FS_event
5
enable TIME
4
enable
MSK_event
3
enable T1
2
enable EX1
1
enable T0
0
enable EX0
10.4.4 INTERRUPT ENABLE REGISTER 1 (IEN1)
Table 18 Interrupt Enable Register 1 (SFR address E8H); reset state 00H
7
6
5
4
3
2
enable RTC enable DSP enable I2C enable EX6 enable EX5 enable EX4
1
enable EX3
0
enable EX2
10.4.5 INTERRUPT REQUEST FLAG REGISTER (IRQ1)
Table 19 Interrupt Request Flag Register 1 (SFR address C0H); reset state 00H; note 1
7
RTC ï¬ag
6
DSP ï¬ag
5
TIME ï¬ag
4
EX6 ï¬ag
3
EX5 ï¬ag
2
EX4 ï¬ag
1
EX3 ï¬ag
0
EX2 ï¬ag
Note
1. The flags of IRQ1 will be set to logic 1 by hardware if the interrupt occurs. They must be cleared by software in the
interrupt service routine.
10.4.6 INTERRUPT POLARITY REGISTER (IX1)
Table 20 Interrupt Polarity Register (SFR address E9H); reset state 00H; note 1
7
spare
6
spare
5
spare
4
3
2
1
0
polarity EX6 polarity EX5 polarity EX4 polarity EX3 polarity EX2
Note
1. A polarity bit set to logic 1 in IX1 will cause the external interrupt to be active HIGH.
10.4.7 INTERRUPT CONTROL REGISTER (INTC)
Table 21 Interrupt Control Register (SFR address C1H); reset state 00H
7
spare
6
spare
5
spare
4
spare
3
spare
2
spare
1
extended
wake-up;
XWU
0
FS ï¬ag
10.4.8 EXTERNAL WAKE-UP DISABLE REGISTER (XWUD)
Table 22 External Wake-up Disable Register (SFR address B9H); reset state 00H
7
RTC XWU
disable
6
DSP XWU
disable
5
TIME XWU
disable
4
EX6 XWU
disable
3
EX5 XWU
disable
2
EX4 XWU
disable
1
EX3 XWU
disable
0
EX2 XWU
disable
2001 Apr 17
29
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