TDA8752B Datasheet, PDF (26/36 Pages) NXP Semiconductors – Triple high-speed Analog-to-Digital Converter 110 Msps ADC

Philips Semiconductors
Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)
Preliminary specification
TDA8752B
SYMBOL
t_d(CLKO)
PARAMETER
delay from CKEXT to
CKADCO
CONDITIONS
INV set to LOW
INV set to HIGH
∆t-t_d(CLKO)
between samples operated in
the same supply and
temperature conditions
Data timing (see Fig.11); f_CLK = 110 MHz; C_L = 10 pF; note 2
t_d(s)
sampling delay time
t_d(o)
output delay time
t_h(o)
output hold time
referenced to CKADCO
3-state output delay time; (see Fig.12)
t_dZH
output enable HIGH
t_dZL
output enable LOW
t_dHZ
output disable HIGH
t_dLZ
output disable LOW
PLL clock output
V_OL
LOW-level output voltage
I_o = 1 mA
V_OH
HIGH-level output voltage
I_o = −1 mA
I_OL
LOW-level output current
V_OL = 0.4 V
I_OH
HIGH-level output current
V_OH = 2.7 V
ADC data outputs
V_OL
LOW-level output voltage
I_o = 1 mA
V_OH
HIGH-level output voltage
I_o = −1 mA
I_OL
LOW-level output current
V_OL = 0.4 V
I_OH
HIGH-level output current
V_OH = 2.7 V
TTL digital inputs (CKREF, COAST, CKEXT, INV, HSYNC and CLP)
V_IL
LOW-level input voltage
V_IH
HIGH-level input voltage
I_IL
LOW-level input current
V_IL = 0.4 V
I_IH
HIGH-level input current
V_IH = 2.7 V
Z_i
input impedance
C_i
input capacitance
3-wire serial bus
t_rst
reset time of the chip before
3-wire communication
t_su
data set-up time
t_h
data hold time
2000 Jan 10
26
MIN.
9.5
−
−
TYP.
MAX.
10.1
10.7
10.1 + -t-^C---2-^L---^K- ^−
0.1
0.3
UNIT
ns
ns
ns
−
−
−
−2
1.5 2.3
−
12
−
10
−
50
−
65
−
0.3
2.4 3.5
−
2
−
−0.4
−
0
2.4
V_CCD
−
2
−
−0.4
−
−
2.0 −
400 −
−
−
−
4
−
4.5
−
600
−
100
−
100
−
ns
−1.5
ns
−
ns
−
ns
−
ns
−
ns
−
ns
0.4
V
−
V
−
mA
−
mA
0.4
V
−
V
−
mA
−
mA
0.8
V
−
V
−
µA
100
µA
−
kΩ
−
pF
−
ns
−
ns
−
ns