TDA8752B Datasheet, PDF (12/36 Pages) NXP Semiconductors – Triple high-speed Analog-to-Digital Converter 110 Msps ADC

Philips Semiconductors
Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)
Preliminary specification
TDA8752B
ADC outputs
ADC outputs are straight binary. An output enable pin
(OE; active LOW) enables the output status between
active and high-impedance (OE = HIGH) to be switched;
it is recommended to load the outputs with a 10 pF
capacitive load. The timing must be checked very carefully
if the capacitive load is more than 10 pF.
Phase-locked loop
The ADCs are clocked either by an internal PLL locked to
the CKREF clock, (all of the PLL is on-chip except the loop
filter capacitance) or an external clock, CKEXT. Selection
is performed via the serial interface bus.
The reference clock (CKREF) range is between
15 and 280 kHz. Consequently, the VCO minimum
frequency is 12 MHz and the maximum frequency
110 MHz for the TDA8752B/8. The gain of the VCO part
can be controlled via the serial interface, depending on the
frequency range to which the PLL is locked.
To increase the bandwidth of the PLL, the charge pump
current, controlled by the serial interface, must also be
increased. The relationship between the frequency and
the current is given by the following equation:
fn = _2--1--π-- _{D-----R-----(}--K-C---O-z----I-₊-P----C-----P-----₎
Where:
f_n = the natural PLL frequency
K_O = the VCO gain
D_R = PLL divider ratio
C_z and C_P = capacitors of the PLL filter.
The other PLL equation is as follows:
fz
=
2----π^-----×^{-----R-1-----}×^{-----C----z--}
and

ξ

=
12--
× -ff-n-z-_{}
Where:
f_z = loop filter zero frequency
R = the chosen resistance for the filter
ξ = the damping factor.
F_O = 0 dB loop gain frequency
Different resistances for the filter can be programmed via
the serial interface. To improve the performances, the PLL
parameters should be chosen so that:
FO= ξ fn ⇒ R IP = ^2------π----K-D----O-R-----F----O---
-Ff--_r-O-_e--_f ≤ 0.15 ⇒ R IP ≤ -0---^,---3-----^π--K---D--O---R-----f--r--e----f = Lim
The values of R and I_p must be chosen so that the product
is the closest to Lim. In the event that there are several
choices, the couple for which the ξ value is the closest to 1
must be chosen.
A software call “PLL calculator’” is available on Philips
Semiconductor Internet site to calculate the best PLL
parameters.
It is possible to control (independently) the phase of the
ADC clock and the phase of an additional clock output
(which could be used to drive a second TDA8752B). For
this, two serial interface-controlled digital phase-shift
controllers are included (controlled by 5-bit registers,
phase shift controller steps are 11.25° each on the whole
PLL frequency range).
CKREF is resynchronized, by the synchro block, on the
CKAO clock. The output is CKREFO (LOW during 8 clock
periods). CKAO is the clock at the output of the phase
selector A. This clock can be used as the clocks for CKBO
and CKADCO. The timing is given in Fig.5.
The COAST pin is used to disconnect the PLL phase
frequency detector during the frame flyback or the
unavailability of the CKREF signal. This signal can
normally be derived from the VSYNC signal.
2000 Jan 10
12