TDA8752B Datasheet, PDF (25/36 Pages) NXP Semiconductors – Triple high-speed Analog-to-Digital Converter 110 Msps ADC

Philips Semiconductors
Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)
Preliminary specification
TDA8752B
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
Phase-locked loop
j_PLL(p-p)
long term PLL jitter
(peak-to-peak value)
DR
divider ratio
f_ref
reference clock frequency
range
f_PLL
output clock frequency range
t_COAST(max) maximum coast mode time
t_recap
PLL recapture time
t_cap
Φ_step
PLL capture time
phase shift step
f_CLK = 110 MHz;
−
see Table 13
100
15
12
−
when coast mode is aborted −
in start-up conditions
−
T_amb = 25 °C
−
0.67
−
−
−
−
3
−
11.25
ADCs
f_s
INL
DNL
ENOB
maximum sampling frequency TDA8752B/8
110 −
DC integral non linearity
from IC analog input to
−
±0.5
digital output; ramp input;
f_CLK = 110 MHz
DC differential non linearity from IC analog input to
−
±0.5
digital output; ramp input;
f_CLK = 110 MHz
effective number of bits
from IC analog input to
−
7.4
digital output; 10 kHz sine
wave input; ramp input;
f_CLK = 110 MHz; note 1
Signal-to-noise ratio
S/N
signal-to-noise ratio
maximum gain;
f_CLK = 110 MHz
minimum gain;
f_CLK = 110 MHz
−
45
−
44
Spurious free dynamic range
SFDR
spurious free dynamic range
maximum gain;
f_CLK = 110 MHz
minimum gain;
f_CLK = 110 MHz
−
60
−
60
Clock timing output (CKADCO, CKBO and CKAO)
η_ext
ADC clock duty cycle
100 MHz output
45
50
f_CLK(max)
maximum clock frequency
110 −
Clock timing input (CKEXT)
f_CLK(max)
maximum clock frequency
t_CPH
clock pulse width HIGH
t_CPL
clock pulse width LOW
110 −
3.6 −
4.5 −
MAX. UNIT
−
ns
4 095
280
kHz
110
MHz
40
lines
−
lines
5
ms
−
deg
−
MHz
±1.5
LSB
±1.0
LSB
−
bits
−
dB
−
dB
−
dB
−
dB
55
%
−
MHz
−
MHz
−
ns
−
ns
2000 Jan 10
25