SC16C2552 Datasheet, PDF (25/38 Pages) NXP Semiconductors – Dual UART with 16-byte transmit and receive FIFOs

Philips Semiconductors
SC16C2552
Dual UART with 16-byte transmit and receive FIFOs
10. Dynamic characteristics
Table 25: AC electrical characteristics
T_amb = −40 °C to +85 °C; V_CC = 2.5 V, 3.3 V or 5.0 V ±10%, unless otherwise specified.
Symbol Parameter
Conditions
2.5 V
3.3 V
Min Max Min Max
t_1w, t_2w
t_3w
clock pulse duration
oscillator/clock frequency
10 -
[1] _-
48
6
-
-
80
t_6s
address set-up time
0
-
0
-
t_6h
address hold time
0
-
0
-
t_7d
IOR delay from chip select
10 -
10 -
t_7w
IOR strobe width
25 pF load
77 -
26 -
t_7h
chip select hold time from IOR
0
-
0
-
t_9d
read cycle delay
25 pF load
20 -
20 -
t_12d
delay from IOR to data
t_12h
data disable time
25 pF load
25 pF load
-
77
-
15
-
26
-
15
t_13d
IOW delay from chip select
t_13w
IOW strobe width
10 -
20
-^[2]
10 -
20
-^[2]
t_13h
chip select hold time from IOW
t_15d
write cycle delay
0
-
[3] ₂₅
-
0
-
25 -
t_16s
data set-up time
20 -
20 -
t_16h
data hold time
15 -
5
-
t_17d
delay from IOW to output
25 pF load
-
100
-
33
t_18d
delay to set interrupt from Modem 25 pF load
-
100
-
24
input
t_19d
delay to reset interrupt from IOR 25 pF load
-
100
-
24
t_20d
delay from stop to set interrupt
-
1
-
1
t_21d
delay from IOR to reset interrupt 25 pF load
-
100
-
29
t_22d
delay from start to set interrupt
-
100
-
45
t_23d
delay from IOW to transmit start
8
24
8
24
t_24d
delay from IOW to reset interrupt
-
100
-
45
t_25d
delay from stop to set RXRDY
-
1
-
1
t_26d
delay from IOR to reset RXRDY
-
100
-
45
t_27d
delay from IOW to set TXRDY
t_28d
delay from start to reset TXRDY
-
100
-
45
-
8
-
8
t_RESET
N
Reset pulse width
baud rate divisor
200 -
40
1
2¹⁶ − 1 1
-
2¹⁶ − 1
5.0 V
Min Max
6
-
80
0
-
0
-
10 -
23 -
0
-
20 -
-
23
-
15
10 -
15 -^[2]
0
-
20 -
15 -
5
-
-
29
-
23
-
23
-
1
-
28
-
40
8
24
-
40
-
1
-
40
-
40
-
8
40 -
1
2¹⁶ − 1
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R_clk
ns
ns
R_clk
ns
R_clk
ns
ns
R_clk
ns
R_clk
[1] Applies to external clock, crystal oscillator max 24 MHz.
[2] IOWstrobe_max = ₂----₍--_B----_a---_u---_d--¹-_r--_a---_t-_e---_m----_a---_x--₎-
= 333 ns (for Baudrate_max = 1.5 Mbits/s)
= 1 µs (for Baudrate_max = 460.8 kbits/s)
= 4 µs (for Baudrate_max = 115.2 kbits/s)
[3] When in both DMA mode 0 and FIFO enable mode, the write cycle delay should be larger than one x₁, clock cycle.
9397 750 11636
Product data
Rev. 03 — 20 June 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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