SC16C2552 Datasheet, PDF (22/38 Pages) NXP Semiconductors – Dual UART with 16-byte transmit and receive FIFOs

Philips Semiconductors
SC16C2552
Dual UART with 16-byte transmit and receive FIFOs
7.9 Scratchpad Register (SPR)
The SC16C2552 provides a temporary data register to store 8 bits of user
information.
7.10 Alternate Function Register (AFR)
This is a read/write register used to select specific modes of MF operation and to
allow both UART register’s sets to be written concurrently.
Table 19: Alternate Function Register bits description
Bit
Symbol
Description
7-3
AFR[7-3]
Not used. All are initialized to logic 0.
2-1
AFR[2-1]
Selects a signal function for output on the MFA, MFB pins. These
signal functions are described as: OP2 (interrupt enable),
BAUDOUT, or TXRDY. Only one signal function can be selected
at a time. See Table 20.
0
AFR[0]
When this bit is set, CPU can write concurrently to the same
register in both UARTs. This function is intended to reduce the
dual UART initialization time. It can be used by CPU when both
channels are initialized to the same state. The external CPU can
set or clear this bit by accessing either register set. When this bit
is set, the Channel Select pin still selects the channel to be
accessed during read operation. Setting or clearing this bit has no
effect on read operations. The user should ensure that LCR[7] of
both channels are in the same state before executing a
concurrent write to the registers at address 0, 1, or 2.
Logic 0 = No concurrent write (normal default condition).
Logic 1 = Register set A and B are written concurrently with a
single external CPU I/O write operation.
Table 20: MFA, MFB function selection
AFR[2]
AFR[1]
MF function
0
0
OP2
0
1
BAUDOUT
1
0
RXRDY
1
1
reserved
9397 750 11636
Product data
Rev. 03 — 20 June 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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