TDA8433 Datasheet, PDF (2/25 Pages) NXP Semiconductors – Deflection processor for computer controlled TV receivers

Philips Semiconductors
Deflection processor for computer
controlled TV receivers
Product specification
TDA8433
FEATURES
• I²C-bus interface
• Input for vertical sync
• Sawtooth generator with amplitude
independent of frequency
• Vertical deflection output stage
driver
• East-west raster correction drive
output
• EHT modulation input
• Changes picture width and height
without affecting geometry.
GENERAL DESCRIPTION
The TDA8433 is an I²C-bus
controlled deflection processor which,
together with a sync processor (e.g.
TDA2579A, see Fig.6), contains the
control and drive functions of the
deflection part in a computer
controlled TV receiver. The TDA8433
replaces all picture geometry settings
which were previously set manually
during manufacture.
QUICK REFERENCE DATA
SYMBOL
V_CC
I_CC
V₂
V₂₁
V₂₄
V_11-13
V_10-13
V_14-13
V₁₅
V₁
PARAMETER
supply voltage (pin 12)
supply current (pin 12)
vertical sync trigger level
vertical feedback (note 1)
DC level
AC level
EHT compensation operating range
inputs for control register data:
not locked to video
at 50 Hz status
at 60 Hz status
HCENT comparator switching level
SDA I²C-bus switching level data input
SCL I²C-bus switching level clock input
device selection where:
Ao = '1'
Ao = '0'
Note to quick reference data
1. VR_in = 0; V-S-corr = 0; V_shift = 20 H; V_ampl = 20 H.
MIN.
10.8
12
−
TYP.
12.0
20
3
MAX.
13.2
27
−
UNIT
V
mA
V
−1.7
1.85
2.05
V
1.65
1.8
1.95
V_P
1.7
−
6
V
−
0.7
0.8 V_CC −
−
−
−
V₁₇
−
3.5
−
3.5
1
V
−
V
0.7 V_CC V
−
V
−
V
−
V
9.0
−
0
−
V_CC
V
2.0
V
ORDERING INFORMATION
EXTENDED TYPE NUMBER
TDA8433
PINS
24
Note
1. SOT101-1; 1996 December 2.
PIN POSITION
DIL
PACKAGE
MATERIAL
plastic
CODE
SOT101⁽¹⁾
August 1991
2