TDA8433 Datasheet, PDF (11/25 Pages) NXP Semiconductors – Deflection processor for computer controlled TV receivers

Philips Semiconductors
Deflection processor for computer
controlled TV receivers
Product specification
TDA8433
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
IN HLOCKN and 50/60 Hz (pin 11)
V₁₁
HLOCKN switching level
V₁₁
switching level where:
LOCKN = '0'
LOCKN = '1'
V₁₁
switching level where:
50/60 Hz = '0'
50/60 Hz = '1'
I₁₁
source current
state 50 Hz
−
0.7
1.0
−
−
−
−
−
0.8 V_CC −
10
25
−
V
−
V
0.4
V
0.7 V_CC V
−
V
35
µA
SDA serial data input (pin 14)
V₁₄
switching level where:
SDA = ‘0’
SDA = ‘1’
I₁₄
sink current
−
−
3.0
−
−
0.5
1.5
V
−
V
10
µA
SCL serial clock input (pin 15)
V₁₅
switching level where:
SDA = ‘0’
SDA = ‘1’
I₁₅
sink current
−
−
3.0
−
−
0.5
1.5
V
−
V
10
µA
Internal supply voltage
V₁₆
maximum allowed load
1 mA load
V₁₇
voltage reference for pin 10 (pin 17)
I₁₇
input load current
4.5
5.0
1.0
−
−
−
5.5
V
V_cc − 1.5 V
2.0
µA
E-W drive output (pin 19; see application information)
V₁₉
output voltage
I₁₉
output current
RR
ripple rejection
R_I
internal resistance
t_R
response time
1 mA load
0.5
−
±1.0 −
24
30
−
1
−
2
11.5
V
±2.0
mA
−
dB
2
kΩ
−
µs
Vertical drive output (pin 20; see application information)
V₂₀
output voltage
I₂₀
output current
RR
ripple rejection
DAC stepsize
1 mA load
note 2
note 3
0.5
−
±1.5 ±2.0
35
40
10
−
10.5
V
−
mA
−
dB
190
%
Vertical feedback (pin 21; see application information: Register 02 = 20H, 03 = 0, 04 = 0, 05 = 20H, 06 = 0)
V₂₁
V_21(p-p)
I₂₁
DC input voltage
AC output voltage (peak-to-peak
value)
input current
note 2
1.7
1.85
1.65 1.8
−
−
2.05
V
1.95
V
−3
µA
August 1991
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