PHP71NQ03LT Datasheet, PDF (2/14 Pages) NXP Semiconductors – TrenchMOS logic level FET

Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOS™ logic level FET
3. Limiting values
Table 2: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
V_DS
V_DGR
V_GS
V_GSM
I_D
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
peak gate-source voltage
drain current (DC)
I_DM
peak drain current
P_tot
total power dissipation
T_stg
storage temperature
T_j
junction temperature
Source-drain diode
25 °C ≤ T_j ≤ 175 °C
25 °C ≤ T_j ≤ 175 °C; R_GS = 20 kΩ
t_p ≤ 50 µs; pulsed; duty cycle = 25 %
T_mb = 25 °C; V_GS = 10 V; Figure 2 and 3
T_mb = 100 °C; V_GS = 10 V; Figure 2
T_mb = 25 °C; pulsed; t_p ≤ 10 µs; Figure 3
T_mb = 25 °C; Figure 1
I_S
source (diode forward) current (DC) T_mb = 25 °C
I_SM
peak source (diode forward) current T_mb = 25 °C; pulsed; t_p ≤ 10 µs
Min
Max Unit
-
30
V
-
30
V
-
±20
V
-
±25
V
-
75
A
-
57.7 A
-
240
A
-
120
W
−55
+175 °C
−55
+175 °C
-
75
A
-
57.7 A
9397 750 09821
Product data
Rev. 01 — 25 June 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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