PDTC123JEF Datasheet, PDF (2/8 Pages) NXP Semiconductors – NPN resistor-equipped transistor

Philips Semiconductors
NPN resistor-equipped transistor
Preliminary specification
PDTC123JEF
FEATURES
• Built-in bias resistors R1 and R2
(typ. 2.2 kΩ and 47 kΩ
respectively)
• Simplification of circuit design
• Reduces number of components
and board space.
APPLICATIONS
• Especially suitable for space
reduction in interface and driver
circuits
• Inverter circuit configurations
without use of external resistors.
DESCRIPTION
NPN resistor-equipped transistor in
an SC-89 (SOT490) plastic package.
PINNING
PIN
DESCRIPTION
1
base/input
2
emitter/ground
3
collector/output
handbook, halfpage ³
3
R1
1
R2
1
2
2
Top view
MAM412
Fig.1 Simplified outline (SC-89; SOT490) and symbol.
1
3
2
MGA893 - 1
MARKING
TYPE
NUMBER
PDTC123JEF
MARKING
CODE
28
Fig.2 Equivalent inverter
symbol.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
V_CBO
V_CEO
V_EBO
V_I
collector-base voltage
collector-emitter voltage
emitter-base voltage
input voltage
positive
negative
I_O
I_CM
P_tot
T_stg
T_j
T_amb
output current (DC)
peak collector current
total power dissipation
storage temperature
junction temperature
operating ambient temperature
CONDITIONS
open emitter
open base
open collector
T_amb ≤ 25 °C; note 1
Note
1. Refer to SC-89 (SOT490) standard mounting conditions.
MIN.
−
−
−
MAX.
50
50
10
UNIT
V
V
V
−
+12
V
−
−5
V
−
100
mA
−
100
mA
−
250
mW
−65
+150
°C
−
150
°C
−65
+150
°C
1999 May 27
2