74HCT3G04 Datasheet, PDF (2/17 Pages) NXP Semiconductors – Inverter

Philips Semiconductors
Inverter
Product specification
74HC3G04; 74HCT3G04
FEATURES
• Wide supply voltage range from 2.0 to 6.0 V
• Symmetrical output impedance
• High noise immunity
• Low power dissipation
• Balanced propagation delays
• Very small 8 pins package
• Output capability: standard
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74HC3G/HCT3G04 is a high-speed Si-gate CMOS
device and is pin compatible with low power Schottky
TTL (LSTTL). Specified in compliance with JEDEC
standard no. 7.
The 74HC3G/HCT3G04 provides three inverting buffers.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f ≤ 6.0 ns.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC3G04 HCT3G04
t_PHL/t_PLH propagation delay nA to nY
C_L = 50 pF; V_CC = 4.5 V 8
10
ns
C_I
input capacitance
1.5
1.5
pF
C_PD
power dissipation capacitance per buffer notes 1 and 2
9
9
pF
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC2 × f_i × N + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
C_L = output load capacitance in pF;
V_CC = supply voltage in Volts;
N = total switching outputs;
∑ (C_L × V_CC2 × f_o) = sum of outputs.
2. For HC3G04 the condition is V_I = GND to V_CC.
For HCT3G04 the condition is V_I = GND to V_CC − 1.5 V.
FUNCTION TABLE
See note 1.
INPUT
nA
L
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
OUTPUT
nY
H
L
2003 Oct 30
2