74HC165 Datasheet, PDF (2/10 Pages) NXP Semiconductors – 8-bit parallel-in/serial-out shift register

Philips Semiconductors
8-bit parallel-in/serial-out shift register
Product specification
74HC/HCT165
FEATURES
• Asynchronous 8-bit parallel load
• Synchronous serial input
• Output capability: standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT165 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT165 are 8-bit parallel-load or serial-in shift
registers with complementary serial outputs (Q₇ and
Q₇) available from the last stage. When the parallel load
(PL) input is LOW, parallel data from the D₀ to
D₇ inputs are loaded into the register asynchronously.
When PL is HIGH, data enters the register serially at the
D_s input and shifts one place to the right
(Q₀ → Q₁ → Q₂, etc.) with each positive-going clock
transition. This feature allows parallel-to-serial converter
expansion by tying the Q₇ output to the D_S input of the
succeeding stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take
place while CP HIGH for predictable operation. Either the
CP or the CE should be HIGH before the
LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
APPLICATIONS
• Parallel-to-serial data conversion
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
t_PHL/ t_PLH
f_max
C_I
C_PD
propagation delay
CP to Q_7, Q₇
PL to Q_7, Q₇
D₇ to Q_7, Q₇
maximum clock frequency
input capacitance
power dissipation capacitance per
package
CONDITIONS
TYPICAL
HC
HCT
C_L = 15 pF; V_CC = 5 V
16
14
15
17
11
11
56
48
3.5
3.5
notes 1 and 2
35
35
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
UNIT
ns
ns
ns
MHz
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2