74HC04 Datasheet, PDF (2/20 Pages) NXP Semiconductors – Hex inverter

Philips Semiconductors
Hex inverter
Product specification
74HC04; 74HCT04
FEATURES
• Complies with JEDEC standard no. 8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74HC/HCT04 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A. The 74HC/HCT04 provide six inverting
buffers.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f ≤ 6.0 ns.
SYMBOL
PARAMETER
CONDITIONS
t_PHL/t_PLH
C_I
C_PD
propagation delay nA to nY
C_L = 15 pF; V_CC = 5 V
input capacitance
power dissipation capacitance per gate notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC2 × f_i × N + Σ(C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
C_L = output load capacitance in pF;
V_CC = supply voltage in Volts;
N = total load switching outputs;
Σ(C_L × V_CC2 × f_o) = sum of the outputs.
2. For 74HC04: the condition is V_I = GND to V_CC.
For 74HCT04: the condition is V_I = GND to V_CC − 1.5 V.
TYPICAL
HC04
7
3.5
21
HCT04
8
3.5
24
UNIT
ns
pF
pF
FUNCTION TABLE
See note 1.
INPUT
nA
L
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
OUTPUT
nY
H
L
2003 Jul 23
2