74F524 Datasheet, PDF (2/14 Pages) NXP Semiconductors – 8-bit register comparator open-collector 3-State

Philips Semiconductors
8-bit register comparator (open collector + 3-State)
Product specification
74F524
FEATURES
• 8-Bit bidirectional register with bus-oriented input-output
• Independent serial input-output to register
• Register bus comparator with ‘equal to’, ‘greater than’ and
‘less than’ outputs
• Cascadable in groups of 8-bits
• Open collector comparator outputs for AND-wired expansion
• Two’s complement or magnitude compare
DESCRIPTION
The 74F524 is an 8-bit bidirectional register with parallel input and
output, plus serial input and output progressing from MSB to LSB.
All data inputs, serial and parallel, are loaded by the rising edge of
the clock. The device functions are controlled by two control lines
(S0, S1) to execute shift, load, hold and read out. An 8-bit
comparator examines the data stored in the registers and on the
data bus. Three true-High, open collector outputs representing
‘register equal to bus’, ‘register greater than bus’ and ‘register less
than bus’ are provided. These outputs can be disabled to the OFF
state by the use of Status Enable (SE). A mode control has also
been provided to allow Two’s Complement as well as magnitude
compare. Linking inputs are provided for expansion to longer words.
PIN CONFIGURATION
S0 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
I/O4 6
I/O5 7
I/O6 8
I/O7 9
GND 10
20 VCC
19 S1
18 SE
17 C/SI
16 C/SO
15 EQ
14 GT
13 LT
12 M
11 CP
SF00970
TYPE
74F524
TYPICAL f_MAX
65MHz
TYPICAL SUPPLY CURRENT
(TOTAL)
110mA
ORDERING INFORMATION
DESCRIPTION
20-pin plastic DIP
COMMERCIAL
RANGE
V_CC = 5V ±10%,
T_amb = 0°C to +70°C
N74F524N
20-pin plastic SOL
N74F524D
PKG DWG #
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
I/On
Parallel data inputs
S0, S1
Mode select inputs
C/SI
Status priority or serial data input
CP
Clock pulse input (active rising edge)
SE
Status enable input (active Low)
M
Compare mode select input
I/On
3-state parallel data outputs
C/SO
Status priority or serial data output
LT
Register less than bus output
EQ
Register equal to bus output
GT
Register greater than bus output
NOTE:
One (1.0) FAST Unit Load (U.L.) is defined as 20µA in the High state and 0.6mA in the Low state.
OC=Open Collector
74F(U.L.)
HIGH/LOW
3.5/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40
50/33
OC/33
OC/33
OC/33
LOAD VALUE
HIGH/LOW
70µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
1.0mA/20mA
OC/20mA
OC/20mA
OC/20mA
1990 Aug 07
2
853–0373 00135