TDA5345HT Datasheet, PDF (18/44 Pages) NXP Semiconductors – 5 V spindle & VCM driver combo

Philips Semiconductors
5 V spindle & VCM driver combo
Preliminary specification
TDA5345HT
Spindle current loop
The spindle current I_Spin is sensed by internal current mirrors and copied to an internal resistor R_SpinLoopGain. The current
loop input is controlled by the internal FLL/PLL speed loop. The transconductance is defined by the following formula
(see Fig.3) :
G_Spin [ ( A) ⁄ ( V) ] = _∆-----V----_S---_p---_i^∆-_n---I_S--^S--_p--^p-_e-ⁱ-_e-ⁿ--_d---_F---_i--_l-_t--_e--_r = _R-----S---_p---_i--_n-5--_L-3-_o---0_o---_p---_G----_a---_i-_n- = _{1----7-5--0-3---00---Ω}--- = 312mA ⁄ V
(1)
The spindle current loop bandwidth is given by the following formula : (gm means transconductance : di/dv)
BW_SpinCurLoop = ^{g----m------O}---^T----^A---2-^×----_â‹--R---_π^------S----_×^{--p------i-C--n}--5----^L-_S^--3--o---_p--0-^o---_i--_n-^p-----_CG-------_o^-a-----_m^-i---^n---_p--^×-_e---_n^g---_s-m------^N---^M----^O----^S-- = 65.5 ⋅ 10^–6 × _C-----S---_p---_i--_n--I-_C-^S--_o-^p--_m-ⁱ-ⁿ--_p---_e---_n---_s
(2)
where the typical values for gm_OTA and gm_NMOS are : gm_OTA = 50 µA/V & gm_NMOS = 2.62 x Sqrt(I_Spin) A/V
BW_SpinCurLoop should be kept <= 20 kHz, whatever the current. Take care of the fact that the higher the current, the higher
the BandWidth => the bandwidth is maximum at Start-Up.
To make sure that the OTA output is 0V when Run/Stop bit = ‘0’, a 30 mV (typ.) offset is introduced inside the OTA. By
this way, we make sure that SpinCompens external capacitor is kept discharged until the next start-up.
Spindle FLL/PLL speed loop :
An internal speed loop is provided, intended to work with 12 poles spindle motors. It is mainly composed of a Frequency
Locked Loop. A Phase Locked Loop can be associated when bit 9 in register #5 (PllOn/Off) is ‘1’. The typical FLL charge
pump current is 500 µA while the typical PLL charge pump current is given in table 7 :
Table 7 PLL charge pump typical current (PllCur[1,0] are bits 8 & 7 in register #5):
PLLCUR[1,0]
00
01
10
11
PLL CH. PUMP CURRENT
0.25 µA
0.5 µA
0.75 µA
1 µA
A 15-bit division factor (Speed[14, 0]) is used to set the required speed split in bits [11, 9] in register #5 and bits [11, 0]
in register #6:
The Speed[14, 0] division factor can be calculated by :
Speed [14, 0] = ^53-- × _{S-----p----i--n---d----l--Ce----S-L---pO----e--C--e--K--d-----(}--r---p---m------₎-
(3)
Where CLOCK is between 10 MHz and 33 MHz.
When the spindle is not running (Run/Stop = ‘0’) the FLL charge pump discharge current is active so that the external
filter is discharged before the next start-up. When the spindle is running (Run/Stop = ‘1’), the speed can be continuously
monitored on pin SpinMechClock (1 pulse per revolution / 50% duty cycle waveform).
SPINDLE / VCM 6-bit current DAC:
An internal 6-bit current DAC is used to limit the spindle start-up current (bit 6 in register #5 : Dac6ToVcm = ‘0’) or to
cancel the VCM loop offset ( Dac6ToVcm = ‘1’).
1999 June 10
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