TDA5345HT Datasheet, PDF (10/44 Pages) NXP Semiconductors – 5 V spindle & VCM driver combo

Philips Semiconductors
5 V spindle & VCM driver combo
Preliminary specification
TDA5345HT
FUNCTIONAL DESCRIPTION
Serial interface
The serial interface is a uni-directional port for writing data to the internal registers of TDA5345HT. Each write is
composed of 16 bits. For data transfer SEN_N is brought low, serial data is presented at SDATA pin, and a serial clock
is applied to the SCLK pin. After the SEN_N pin goes low, the first 16 pulses applied to the SCLK pin shifts the data
presented at the SDATA pin into an internal shift register on the rising edge of each clock. An internal counter prevents
more than 16 bits from being shifted into the register. The data in the shift register is latched when SEN_N goes high. If
less than 16 clock pulses are provided before SEN_N goes high, the data transfer is aborted.
All transfers are shifted into the serial port MSB first. The first 4 bits of the transfer determine the internal register to be
accessed. The other 12 bits contain the programming data. During sleep modes, the serial port remains active and
register programming data is retained.
SEN_N
Address
T_st
Receive data
T_su
T_hd
T_ex
SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SDATA A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Write to TDA5345HT
Fig.6 Serial port timing information.
Table 1 Address of registers
A3
A2
A1
A0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
REG.
0
1
2
3
4
5
6
7
8
9
DESCRIPTION
clock dividers programmation, spindle mode control
start-up,comdelim & watch-dog delays
blank delay, bandgap adjust, 3-step retract param (begin)
3-step retract parameters (end)
fly-back slope, shock sensor threshold & sleep control bits
speed factor (MSBs), PLL control and 6-bit DAC
speed factor(LSBs)
Vcm 12-bit DAC (low gain)
Vcm 12-bit DAC (high gain)
shock sensor threshold
1999 June 10
10