TDA5345HT Datasheet, PDF (11/44 Pages) NXP Semiconductors – 5 V spindle & VCM driver combo

Philips Semiconductors
5 V spindle & VCM driver combo
Preliminary specification
TDA5345HT
Table 2 Serial Interface REGISTERS floorplan
BIT\
REG
0
1
2
3
4
5
6
7
8
9
11
10
9
8
7
6
5
4
3
2
1
0
RegNeg RegNeg RegNeg Presc
Clk2
Clk1
Clk0 Factor1
[0]
[1]
[0]
[0]
StartUp StartUp StartUp StartUp
Delay3 Delay2 Delay1 Delay0
Blank Blank Blank Blank
Delay3 Delay2 Delay1 Delay0
T_Full T_Full T_Full T_Slow
Power2 Power1 Power0 Ret5
FlyBack FlyBack Shock Shock
Slope1 Slope0 Thresh1 Thresh0
Speed Speed Speed PllCur
bit14 bit13 bit12
1
Speed
bit11
Dac12a
bit11
Dac12b
bit11
Speed
bit10
Dac12a
bit10
Dac12b
bit10
Shock
Thresh2
[0]
Speed
bit9
Dac12a
bit9
Dac12b
bit9
Speed
bit8
Dac12a
bit8
Dac12b
bit8
Presc
Factor0
[0]
ComDe
Lim3
DigOut
Mux
[1]
T_Slow
Ret4
Vcm
Retract
[0]
PllCur
0
Speed
bit7
Dac12a
bit7
Dac12b
bit7
BiasCT
[0]
ComDe
Lim2
BdGap
Adj2
[0]
T_Slow
Ret3
Vcm
Sleep
[1]
Dac6
ToVCM
[0]
Speed
bit6
Dac12a
bit6
Dac12b
bit6
Run/
Stop
[0]
ComDe
Lim1
BdGap
Adj1
[0]
T_Slow
Ret2
Dac12
Sleep
[1]
Dac6
bit5
Speed
bit5
Dac12a
bit5
Dac12b
bit5
Pll Manual
Enable
[0]
[0]
ComDe Watch
Lim0 Dog3
BdGAp VcmRet
Adj0 SoftRis
[0]
T_Slow T_Slow
Ret1 Ret0
RegNeg Shock
Sleep Sleep
[1]
[1]
Dac6
bit4
Dac6
bit3
Speed
bit4
Dac12a
bit4
Dac12b
bit4
Speed
bit3
Dac12a
bit3
Dac12b
bit3
Man
Com2
Watch
Dog2
Vretract
2
T_Vcm
Brake2
Spin
Sleep
[1]
Dac6
bit2
Speed
bit2
Dac12a
bit
Dac12b
bit2
Man
Com1
Watch
Dog1
Vretract
1
T_Vcm
Brake1
Reg3v3
Enable
[0]
Dac6
bit1
Speed
bit1
Dac12a
bit1
Dac12b
bit1
Man
Com0
Watch
Dog0
Vretract
0
T_Vcm
Brake0
Temp
Select
[0]
Dac6
bit0
Speed
bit0
Dac12a
bit0
Dac12b
bit0
Note:
1. [1] (or [0]) means that the bit is set to 1 (or 0) when PorN is low => default value at power up.
2. Use register 7 (Dac12a) for low VCM loop gain and register 8 (Dac12b) for high gain.
Control bits:
REGISTER #0:
Bits [11, 9] (RegNegClk[2, 0]): The Negative supply (-3V) regulator needs a 500 kHz clock. A programmable divider
genreates this frequency from the external clock ([15-33] Mhz). Programmation is on 3 bits.
Bits [8, 7] (PrescFactor[1, 0]): used to select the prescaler division factor (see next section: “commutation control”).
Bit 6 (BiasCT): used to bias the spindle centre tap at Vdd5/2 when the spindle outputs are disabled (Run/Stop = 0). The
back-EMF comparator remains operational when BiasCT = 1, to check if the spindle is running for instance.
Bit 5 (Run/Stop): after the power supply is turned on and PorN is high, the motor will start spinning when Run/Stop is
set to ‘1’. The spindle power output starts from state code 0 (see table 3). The motor will stop when this bit is set to ‘0’.
The 3 spindle power outputs are then switched off. No brake is applied.
bit 4 (PllEnable): enables the PLL to improve the speed accuracy.
Bit 3 (Manual): selects the manual commutation mode (Run/Stop bit also needs to be high). When getting out of the
manual mode (=> Manual = ‘0’) and keeping the Run/Stop bit high, the internal commutation block will start from the last
state programmed in manual mode.
Bits [2, 0] (ManCom[2, 0]): control the commutation in manual mode when Run/Stop = 1 & Manual = 1.
1999 June 10
11