TDA8005 Datasheet, PDF (17/32 Pages) NXP Semiconductors – Low-power smart card coupler

Philips Semiconductors
Low-power smart card coupler
Product specification
TDA8005
I/O buffer modes (see Fig.8)
The following are the I/O buffer modes:
1. I/O buffer disabled by ENIO.
2. I/O buffer in input, 20 kΩ pull-up resister connected
between I/O and V_CC, I/O masked till 200 clock pulses.
3. I/O buffer in input, 20 kΩ pull-up resister connected
between I/O and V_CC, I/O is sampled every 31 clock
pulses.
4. I/O buffer in output, 20 kΩ pull-up resister connected
between I/O and V_CC.
5. I/O buffer in output, I/O is pulled LOW by the N
transistor of the buffer.
6. I/O buffer in output, I/O is strongly HIGH or LOW by the
P or N transistor.
Output ports extension
In the LQFP64 version, 6 auxiliary output ports may be
used for low frequency tasks (for example, keyboard
scanning). These ports are push-pull output types (cf use
in software document).
Activation sequence
When the card is inactive, V_CC, CLK, RST and I/O are
LOW, with low impedance with respect to GND. The
step-up converter is stopped. The I/O is configured in the
reception mode with a high impedance path to the ISO
UART, subsequently no spurious pulse from the card
during power-up will be taken into account until I/O is
enabled. When everything is satisfactory (voltage supply,
card present, no hardware problems), the microcontroller
may initiate an activation sequence by setting START
LOW (t₀):
• The step-up converter is started (t₁)
• LIS signal is disabled by ENLI, and V_CC starts rising from
0 to 5 V with a controlled rise time of 0.1 V/µs typically
(t₂)
• I/O buffer is enabled (t₃)
• Clock is sent to the card (t₄)
• RST buffer is enabled (t₅).
In order to allow a precise count of clock pulses during
ATR, a defined time window (t₃; t₅) is opened where the
clock may be sent to the card by means of RSTIN. Beyond
this window, RSTIN has no more action on clock, and only
monitors the cards RST contact (RST is the inverse of
RSTIN).
The sequencer is clocked by f_INT/64 which leads to a time
interval T of 25 µs typical. Thus t₁ = 0 to ¹â„₆₄T,
t₂ = t₁ + ¹â„₂3T, t₃ = t₁ + 4T, t₄ = t₃ to t₅ and t₅ = t₁ + 7T
(see Fig.9).
Deactivation sequence (see Fig.10)
When the session is completed, the microcontroller sets
START HIGH. The circuit then executes an automatic
deactivation sequence:
• Card reset (RST falls LOW) at t₁₀
• Clock is stopped at t₁₁
• I/O becomes high impedance to the ISO UART (t₁₂)
• V_CC falls to 0 V with typical 0.1 V/µs slew rate (t₁₃)
• The step-up converter is stopped and CLK, RST, V_CC
and I/O become low impedance to GND (t₁₄).
• t₁₀ < ¹â„₆₄T; t₁₁ = t₁₀ + ¹â„₂T; t₁₂ = t₁₀ + T; t₁₃ = t₁₀ + ¹â„₂3T;
t₁₄ = t₁₀ + 5T.
Protections
Main hardware fault conditions are monitored by the circuit
• Overcurrent on V_CC
• Short circuits between V_CC and other contacts
• Card take-off during transaction.
When one of these problems is detected, the security logic
block pulls the interrupt line OFF LOW, in order to warn the
microcontroller, and initiates an automatic deactivation of
the contacts. When the deactivation has been completed,
the OFF line returns HIGH, except if the problem was due
to a card extraction in which case it remains LOW till a card
is inserted.
1996 Sep 25
17