TDA8005 Datasheet, PDF (14/32 Pages) NXP Semiconductors – Low-power smart card coupler

Philips Semiconductors
Low-power smart card coupler
Product specification
TDA8005
ISO UART
The ISO UART handles all the specific requirements
defined in ISO T = 0 protocol type. It is clocked with the
cards clock, which gives the f_clk/31 sampling rate for start
bit detection (the start bit is detected at the first LOW level
on I/O) and the f_clk/372 frequency for ETU timing (in the
reception mode the bit is sampled at ¹â„₂ETU). It also allows
the cards clock frequency changes without interfering with
the baud rate.
This hardware UART allows operating of the
microcontroller at low frequency, thus lowering EM
radiations and power consumption. It also frees the
microcontroller of fastidious conversions and real time jobs
thereby allowing the control of higher level tasks.
The following occurs in the reception mode (see Fig.6):
• Detection of the inverse or direct convention at the begin
of ATR.
• Automatic convention setting, so the microcontroller
only receives characters in direct convention.
• Parity checking and automatic request for character
repetition in case of error (reception is possible at
12 ETU).
In the transmission mode (see Fig.7):
• Transmission according to the convention detected
during ATR, consequently the microcontroller only has
to send characters in direct convention. Transmission of
the next character may start at 12 ETU in the event of no
error or 13 ETU in case of error.
• Parity calculation and detection of repetition request
from the card in the event of error.
• The bit LCT (Last Character to Transmit) allows fast
reconfiguration for receiving the answer 12 ETU after
the start bit of the last transmitted character.
The ISO UART status register can inform which event has
caused an interrupt. (Buffer full, buffer empty, parity error
detected etc.) cf Peripheral Interface.
This register is reset when the microcontroller reads the
status out of it.
The ISO UART configuration register enables the
microcontroller to configure the ISO UART. cf Peripheral
Interface.
After power-on, all ISO UART registers are reset.
The ISO UART is configured in the reception mode. When
the microcontroller wants to start a session, it sets the bits
START SESSION and RESET ISO UART in UART
CONFIGURATION and then sets START LOW. When the
first start bit on I/O is detected (sampling rate f_clk/31), the
UART sets the bit US2 (First Start Detect) in the status
register which gives an interrupt on INT0 one CLK pulse
later.
The convention is recognized on the first character of the
ATR and the UART configures itself in order to exchange
direct data without parity processing with the
microcontroller whatever the convention of the card is.
The bit START SESSION must be reset by software. At
the end of every character, the UART tests the parity and
resets what is necessary for receiving another character.
If no parity error is detected, the UART sets the bit US1
(BUFFER FULL) in the STATUS REGISTER which warns
the microcontroller it has to read the character before the
reception of the next one has been completed. The
STATUS REGISTER is reset when read from the
controller.
If a parity error has been detected, the UART pulls the I/O
line LOW between 10.5 and 12 ETU. It also sets the bits
BUFFER FULL and US3 (parity error during reception) in
the STATUS REGISTER which warns the microcontroller
that an error has occurred. The card is supposed to repeat
the previous character.
1996 Sep 25
14