UJA1078ATW Datasheet, PDF (16/54 Pages) NXP Semiconductors – High-speed CAN/dual LIN core system basis chip

NXP Semiconductors
UJA1078A
High-speed CAN/dual LIN core system basis chip
6.2.6 Int_Status register
Table 7. Int_Status register^[1]
Bit Symbol Access Power-on Description
default
15:13 A2, A1, A0 R
011
register address
12
RO
R/W 0
access status
0: register set to read/write
1: register set to read only
11
V1UI
R/W 0
V1 undervoltage interrupts
0: no V1 undervoltage warning interrupt pending
1: V1 undervoltage warning interrupt pending
10
V2UI
R/W 0
V2 undervoltage interrupts
0: no V2 undervoltage warning interrupt pending
1: V2 undervoltage warning interrupt pending
9
LWI1
R/W 0
LIN wake-up interrupt 1
0: no LIN1 wake-up interrupt pending
1: LIN1 wake-up interrupt pending
8
LWI2
R/W 0
LIN wake-up interrupt 2
0: no LIN2 wake-up interrupt pending
1: LIN2 wake-up interrupt pending
7
CI
R/W 0
cyclic interrupt
0: no cyclic interrupt pending
1: cyclic interrupt pending
6
WI1
R/W 0
wake-up interrupt 1
0: no wake-up interrupt 1 pending
1: wake-up interrupt 1 pending
5
POSI
R/W 1
power-on status interrupt
0: no power-on interrupt pending
1: power-on interrupt pending
4
WI2
R/W 0
wake-up interrupt 2
0: no wake-up interrupt 2 pending
1: wake-up interrupt 2 pending
3
CWI
R/W 0
CAN wake-up interrupt
0: no CAN wake-up interrupt pending
1: CAN wake-up interrupt pending
2:0 reserved R
000
[1] An interrupt can be cleared by writing 1 to the relevant bit in the Int_Status register.
UJA1078A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 28 January 2011
© NXP B.V. 2011. All rights reserved.
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